Commit be85831d authored by Joakim Zhang's avatar Joakim Zhang Committed by Shawn Guo
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arm64: dts: imx8qm: add can node in devicetree 



Add CAN node for imx8qm in devicetree.

Unlike on the i.MX 8QXP where the flexcan clocks are shared between
multiple CAN instances, the i.MX 8QM has separate flexcan clock slices.

Signed-off-by: default avatarJoakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 5e7d5b02

arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi

+44 −0
Original line number Diff line number Diff line
@@ -16,6 +16,50 @@ uart4_lpcg: clock-controller@5a4a0000 { 
				     "uart4_lpcg_ipg_clk";

		power-domains = <&pd IMX_SC_R_UART_4>;

	};



	can1_lpcg: clock-controller@5ace0000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5ace0000 0x10000>;

		#clock-cells = <1>;

		clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>,

			 <&dma_ipg_clk>, <&dma_ipg_clk>;

		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;

		clock-output-names = "can1_lpcg_pe_clk",

				     "can1_lpcg_ipg_clk",

				     "can1_lpcg_chi_clk";

		power-domains = <&pd IMX_SC_R_CAN_1>;

	};



	can2_lpcg: clock-controller@5acf0000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5acf0000 0x10000>;

		#clock-cells = <1>;

		clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>,

			 <&dma_ipg_clk>, <&dma_ipg_clk>;

		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;

		clock-output-names = "can2_lpcg_pe_clk",

				     "can2_lpcg_ipg_clk",

				     "can2_lpcg_chi_clk";

		power-domains = <&pd IMX_SC_R_CAN_2>;

	};

};



&flexcan1 {

	fsl,clk-source = /bits/ 8 <1>;

};



&flexcan2 {

	clocks = <&can1_lpcg 1>,

		 <&can1_lpcg 0>;

	assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;

	fsl,clk-source = /bits/ 8 <1>;

};



&flexcan3 {

	clocks = <&can2_lpcg 1>,

		 <&can2_lpcg 0>;

	assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;

	fsl,clk-source = /bits/ 8 <1>;

};



&lpuart0 {