Commit bebc0762 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: switch to new amdgpu_nbio structure 



no functional change, just switch to new structures

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 078ef4e9

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+4 −59
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ 
#include "amdgpu_gmc.h"

#include "amdgpu_gfx.h"

#include "amdgpu_sdma.h"

#include "amdgpu_nbio.h"

#include "amdgpu_dm.h"

#include "amdgpu_virt.h"

#include "amdgpu_csa.h"
@@ -644,69 +645,11 @@ typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 
typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);





/*

 * amdgpu nbio functions

 *

 */

struct nbio_hdp_flush_reg {

	u32 ref_and_mask_cp0;

	u32 ref_and_mask_cp1;

	u32 ref_and_mask_cp2;

	u32 ref_and_mask_cp3;

	u32 ref_and_mask_cp4;

	u32 ref_and_mask_cp5;

	u32 ref_and_mask_cp6;

	u32 ref_and_mask_cp7;

	u32 ref_and_mask_cp8;

	u32 ref_and_mask_cp9;

	u32 ref_and_mask_sdma0;

	u32 ref_and_mask_sdma1;

	u32 ref_and_mask_sdma2;

	u32 ref_and_mask_sdma3;

	u32 ref_and_mask_sdma4;

	u32 ref_and_mask_sdma5;

	u32 ref_and_mask_sdma6;

	u32 ref_and_mask_sdma7;

};



struct amdgpu_mmio_remap {

	u32 reg_offset;

	resource_size_t bus_addr;

};



struct amdgpu_nbio_funcs {

	const struct nbio_hdp_flush_reg *hdp_flush_reg;

	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);

	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);

	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);

	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);

	u32 (*get_rev_id)(struct amdgpu_device *adev);

	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);

	void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);

	u32 (*get_memsize)(struct amdgpu_device *adev);

	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,

			bool use_doorbell, int doorbell_index, int doorbell_size);

	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,

				   int doorbell_index, int instance);

	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,

					 bool enable);

	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,

						  bool enable);

	void (*ih_doorbell_range)(struct amdgpu_device *adev,

				  bool use_doorbell, int doorbell_index);

	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,

						 bool enable);

	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,

						bool enable);

	void (*get_clockgating_state)(struct amdgpu_device *adev,

				      u32 *flags);

	void (*ih_control)(struct amdgpu_device *adev);

	void (*init_registers)(struct amdgpu_device *adev);

	void (*detect_hw_virt)(struct amdgpu_device *adev);

	void (*remap_hdp_registers)(struct amdgpu_device *adev);

};



struct amdgpu_df_funcs {

	void (*sw_init)(struct amdgpu_device *adev);

	void (*enable_broadcast_mode)(struct amdgpu_device *adev,
@@ -921,6 +864,9 @@ struct amdgpu_device { 
	u32				cg_flags;

	u32				pg_flags;



	/* nbio */

	struct amdgpu_nbio		nbio;



	/* gfx */

	struct amdgpu_gfx		gfx;
@@ -974,7 +920,6 @@ struct amdgpu_device { 
	/* soc15 register offset based on ip, instance and  segment */

	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];



	const struct amdgpu_nbio_funcs	*nbio_funcs;

	const struct amdgpu_df_funcs	*df_funcs;

	const struct amdgpu_mmhub_funcs	*mmhub_funcs;

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

+8 −8
Original line number Diff line number Diff line
@@ -99,8 +99,8 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev, 
	unsigned long flags, address, data;

	uint32_t ficadl_val, ficadh_val;



	address = adev->nbio_funcs->get_pcie_index_offset(adev);

	data = adev->nbio_funcs->get_pcie_data_offset(adev);

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
@@ -122,8 +122,8 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, 
{

	unsigned long flags, address, data;



	address = adev->nbio_funcs->get_pcie_index_offset(adev);

	data = adev->nbio_funcs->get_pcie_data_offset(adev);

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
@@ -150,8 +150,8 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev, 
{

	unsigned long flags, address, data;



	address = adev->nbio_funcs->get_pcie_index_offset(adev);

	data = adev->nbio_funcs->get_pcie_data_offset(adev);

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	WREG32(address, lo_addr);
@@ -172,8 +172,8 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr, 
{

	unsigned long flags, address, data;



	address = adev->nbio_funcs->get_pcie_index_offset(adev);

	data = adev->nbio_funcs->get_pcie_data_offset(adev);

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	WREG32(address, lo_addr);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+7 −7
Original line number Diff line number Diff line
@@ -2421,7 +2421,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 
	}



	if (amdgpu_emu_mode == 1)

		adev->nbio_funcs->hdp_flush(adev, NULL);

		adev->nbio.funcs->hdp_flush(adev, NULL);



	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);

	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -2491,7 +2491,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 
	}



	if (amdgpu_emu_mode == 1)

		adev->nbio_funcs->hdp_flush(adev, NULL);

		adev->nbio.funcs->hdp_flush(adev, NULL);



	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);

	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
@@ -2560,7 +2560,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 
	}



	if (amdgpu_emu_mode == 1)

		adev->nbio_funcs->hdp_flush(adev, NULL);

		adev->nbio.funcs->hdp_flush(adev, NULL);



	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);

	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -2881,7 +2881,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 
	}



	if (amdgpu_emu_mode == 1)

		adev->nbio_funcs->hdp_flush(adev, NULL);

		adev->nbio.funcs->hdp_flush(adev, NULL);



	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);

	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
@@ -4335,7 +4335,7 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 
{

	struct amdgpu_device *adev = ring->adev;

	u32 ref_and_mask, reg_mem_engine;

	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;

	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;



	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

		switch (ring->me) {
@@ -4355,8 +4355,8 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 
	}



	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,

			       adev->nbio_funcs->get_hdp_flush_req_offset(adev),

			       adev->nbio_funcs->get_hdp_flush_done_offset(adev),

			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),

			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),

			       ref_and_mask, ref_and_mask, 0x20);

}

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −3
Original line number Diff line number Diff line
@@ -4972,7 +4972,7 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 
{

	struct amdgpu_device *adev = ring->adev;

	u32 ref_and_mask, reg_mem_engine;

	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;

	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;



	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

		switch (ring->me) {
@@ -4992,8 +4992,8 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 
	}



	gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,

			      adev->nbio_funcs->get_hdp_flush_req_offset(adev),

			      adev->nbio_funcs->get_hdp_flush_done_offset(adev),

			      adev->nbio.funcs->get_hdp_flush_req_offset(adev),

			      adev->nbio.funcs->get_hdp_flush_done_offset(adev),

			      ref_and_mask, ref_and_mask, 0x20);

}

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+3 −3
Original line number Diff line number Diff line
@@ -278,7 +278,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 
	int r;



	/* flush hdp cache */

	adev->nbio_funcs->hdp_flush(adev, NULL);

	adev->nbio.funcs->hdp_flush(adev, NULL);



	mutex_lock(&adev->mman.gtt_window_lock);
@@ -557,7 +557,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 


	/* size in MB on si */

	adev->gmc.mc_vram_size =

		adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;

		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;

	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;

	adev->gmc.visible_vram_size = adev->gmc.aper_size;
@@ -794,7 +794,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 
	WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);



	/* Flush HDP after it is initialized */

	adev->nbio_funcs->hdp_flush(adev, NULL);

	adev->nbio.funcs->hdp_flush(adev, NULL);



	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?

		false : true;