Loading Documentation/ABI/testing/sysfs-bus-event_source-devices-iommu 0 → 100644 +37 −0 Original line number Diff line number Diff line What: /sys/bus/event_source/devices/dmar*/format Date: Jan 2023 KernelVersion: 6.3 Contact: Kan Liang <kan.liang@linux.intel.com> Description: Read-only. Attribute group to describe the magic bits that go into perf_event_attr.config, perf_event_attr.config1 or perf_event_attr.config2 for the IOMMU pmu. (See also ABI/testing/sysfs-bus-event_source-devices-format). Each attribute in this group defines a bit range in perf_event_attr.config, perf_event_attr.config1, or perf_event_attr.config2. All supported attributes are listed below (See the VT-d Spec 4.0 for possible attribute values):: event = "config:0-27" - event ID event_group = "config:28-31" - event group ID filter_requester_en = "config1:0" - Enable Requester ID filter filter_domain_en = "config1:1" - Enable Domain ID filter filter_pasid_en = "config1:2" - Enable PASID filter filter_ats_en = "config1:3" - Enable Address Type filter filter_page_table_en= "config1:4" - Enable Page Table Level filter filter_requester_id = "config1:16-31" - Requester ID filter filter_domain = "config1:32-47" - Domain ID filter filter_pasid = "config2:0-21" - PASID filter filter_ats = "config2:24-28" - Address Type filter filter_page_table = "config2:32-36" - Page Table Level filter What: /sys/bus/event_source/devices/dmar*/cpumask Date: Jan 2023 KernelVersion: 6.3 Contact: Kan Liang <kan.liang@linux.intel.com> Description: Read-only. This file always returns the CPU to which the IOMMU pmu is bound for access to all IOMMU pmu performance monitoring events. Documentation/devicetree/bindings/iommu/apple,dart.yaml +1 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ properties: compatible: enum: - apple,t8103-dart - apple,t8110-dart - apple,t6000-dart reg: Loading Documentation/devicetree/bindings/iommu/arm,smmu.yaml +57 −9 Original line number Diff line number Diff line Loading @@ -36,13 +36,17 @@ properties: - enum: - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 - qcom,sdm670-smmu-500 - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8150-smmu-500 Loading @@ -52,14 +56,6 @@ properties: - const: qcom,smmu-500 - const: arm,mmu-500 - description: Qcom SoCs implementing "arm,mmu-500" (non-qcom implementation) deprecated: true items: - enum: - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - const: arm,mmu-500 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) deprecated: true items: Loading @@ -84,6 +80,7 @@ properties: items: - enum: - qcom,sc7280-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: qcom,adreno-smmu - const: arm,mmu-500 Loading Loading @@ -201,7 +198,8 @@ properties: maxItems: 7 power-domains: maxItems: 1 minItems: 1 maxItems: 3 nvidia,memory-controller: description: | Loading Loading @@ -366,6 +364,56 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. # Disallow clocks for all other platforms with specific compatibles - if: properties: compatible: contains: enum: - cavium,smmu-v2 - marvell,ap806-smmu-500 - nvidia,smmu-500 - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 - qcom,sdm670-smmu-500 - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 then: properties: clock-names: false clocks: false - if: properties: compatible: contains: const: qcom,sm6375-smmu-500 then: properties: power-domains: items: - description: SNoC MMU TBU RT GDSC - description: SNoC MMU TBU NRT GDSC - description: SNoC TURING MMU TBU0 GDSC required: - power-domains else: properties: power-domains: maxItems: 1 examples: - |+ /* SMMU with stream matching or stream indexing */ Loading Documentation/devicetree/bindings/iommu/qcom,iommu.txt +1 −0 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ to non-secure vs secure interrupt line. - compatible : Should be one of: "qcom,msm8916-iommu" "qcom,msm8953-iommu" Followed by "qcom,msm-iommu-v1". Loading Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml +1 −0 Original line number Diff line number Diff line Loading @@ -49,6 +49,7 @@ properties: - enum: - renesas,ipmmu-r8a779a0 # R-Car V3U - renesas,ipmmu-r8a779f0 # R-Car S4-8 - renesas,ipmmu-r8a779g0 # R-Car V4H - const: renesas,rcar-gen4-ipmmu-vmsa # R-Car Gen4 reg: Loading Loading
Documentation/ABI/testing/sysfs-bus-event_source-devices-iommu 0 → 100644 +37 −0 Original line number Diff line number Diff line What: /sys/bus/event_source/devices/dmar*/format Date: Jan 2023 KernelVersion: 6.3 Contact: Kan Liang <kan.liang@linux.intel.com> Description: Read-only. Attribute group to describe the magic bits that go into perf_event_attr.config, perf_event_attr.config1 or perf_event_attr.config2 for the IOMMU pmu. (See also ABI/testing/sysfs-bus-event_source-devices-format). Each attribute in this group defines a bit range in perf_event_attr.config, perf_event_attr.config1, or perf_event_attr.config2. All supported attributes are listed below (See the VT-d Spec 4.0 for possible attribute values):: event = "config:0-27" - event ID event_group = "config:28-31" - event group ID filter_requester_en = "config1:0" - Enable Requester ID filter filter_domain_en = "config1:1" - Enable Domain ID filter filter_pasid_en = "config1:2" - Enable PASID filter filter_ats_en = "config1:3" - Enable Address Type filter filter_page_table_en= "config1:4" - Enable Page Table Level filter filter_requester_id = "config1:16-31" - Requester ID filter filter_domain = "config1:32-47" - Domain ID filter filter_pasid = "config2:0-21" - PASID filter filter_ats = "config2:24-28" - Address Type filter filter_page_table = "config2:32-36" - Page Table Level filter What: /sys/bus/event_source/devices/dmar*/cpumask Date: Jan 2023 KernelVersion: 6.3 Contact: Kan Liang <kan.liang@linux.intel.com> Description: Read-only. This file always returns the CPU to which the IOMMU pmu is bound for access to all IOMMU pmu performance monitoring events.
Documentation/devicetree/bindings/iommu/apple,dart.yaml +1 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ properties: compatible: enum: - apple,t8103-dart - apple,t8110-dart - apple,t6000-dart reg: Loading
Documentation/devicetree/bindings/iommu/arm,smmu.yaml +57 −9 Original line number Diff line number Diff line Loading @@ -36,13 +36,17 @@ properties: - enum: - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 - qcom,sdm670-smmu-500 - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8150-smmu-500 Loading @@ -52,14 +56,6 @@ properties: - const: qcom,smmu-500 - const: arm,mmu-500 - description: Qcom SoCs implementing "arm,mmu-500" (non-qcom implementation) deprecated: true items: - enum: - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - const: arm,mmu-500 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) deprecated: true items: Loading @@ -84,6 +80,7 @@ properties: items: - enum: - qcom,sc7280-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: qcom,adreno-smmu - const: arm,mmu-500 Loading Loading @@ -201,7 +198,8 @@ properties: maxItems: 7 power-domains: maxItems: 1 minItems: 1 maxItems: 3 nvidia,memory-controller: description: | Loading Loading @@ -366,6 +364,56 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. # Disallow clocks for all other platforms with specific compatibles - if: properties: compatible: contains: enum: - cavium,smmu-v2 - marvell,ap806-smmu-500 - nvidia,smmu-500 - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 - qcom,sdm670-smmu-500 - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 then: properties: clock-names: false clocks: false - if: properties: compatible: contains: const: qcom,sm6375-smmu-500 then: properties: power-domains: items: - description: SNoC MMU TBU RT GDSC - description: SNoC MMU TBU NRT GDSC - description: SNoC TURING MMU TBU0 GDSC required: - power-domains else: properties: power-domains: maxItems: 1 examples: - |+ /* SMMU with stream matching or stream indexing */ Loading
Documentation/devicetree/bindings/iommu/qcom,iommu.txt +1 −0 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ to non-secure vs secure interrupt line. - compatible : Should be one of: "qcom,msm8916-iommu" "qcom,msm8953-iommu" Followed by "qcom,msm-iommu-v1". Loading
Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml +1 −0 Original line number Diff line number Diff line Loading @@ -49,6 +49,7 @@ properties: - enum: - renesas,ipmmu-r8a779a0 # R-Car V3U - renesas,ipmmu-r8a779f0 # R-Car S4-8 - renesas,ipmmu-r8a779g0 # R-Car V4H - const: renesas,rcar-gen4-ipmmu-vmsa # R-Car Gen4 reg: Loading