Commit bef96521 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.16-tag1' of... 

Merge tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add GPU and USB2 clocks and resets on Renesas RZ/V2H(P)
 - Add support for the Renesas RZ/V2N (R9A09G056) SoC
 - Add GPU clocks and resets on Renesas RZ/G3E

* tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (22 commits)
  clk: renesas: r9a09g057: Add clock and reset entries for USB2
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
  clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
  clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
  clk: renesas: rzv2h: Support static dividers without RMW
  clk: renesas: rzv2h: Add macro for defining static dividers
  clk: renesas: rzv2h: Add support for static mux clocks
  clk: renesas: r9a09g047: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Fix a typo
  clk: renesas: rzv2h: Add support for RZ/V2N SoC
  clk: renesas: rzv2h: Sort compatible list based on SoC part number
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
  clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
  clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()
  clk: renesas: r9a09g057: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Rename PLL field macros for consistency
  clk: renesas: rzv2h: Add support for enabling PLLs
  ...
parents 0af2f6be 93f28781

Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

+3 −2
Original line number Diff line number Diff line
@@ -4,13 +4,13 @@ 
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)

title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles

  On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles

  generation and control of clock signals for the IP modules, generation and

  control of resets, and control over booting, low power consumption and power

  supply domains.
@@ -19,6 +19,7 @@ properties: 
  compatible:

    enum:

      - renesas,r9a09g047-cpg # RZ/G3E

      - renesas,r9a09g056-cpg # RZ/V2N

      - renesas,r9a09g057-cpg # RZ/V2H



  reg:

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+2 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ properties: 
              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}

              - renesas,r9a08g045-pinctrl # RZ/G3S

              - renesas,r9a09g047-pinctrl # RZ/G3E

              - renesas,r9a09g056-pinctrl # RZ/V2N

              - renesas,r9a09g057-pinctrl # RZ/V2H(P)



      - items:
@@ -145,6 +146,7 @@ allOf: 
          contains:

            enum:

              - renesas,r9a09g047-pinctrl

              - renesas,r9a09g056-pinctrl

              - renesas,r9a09g057-pinctrl

    then:

      properties:

Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ properties: 
    items:

      - enum:

          - renesas,r9a09g047-sys # RZ/G3E

          - renesas,r9a09g056-sys # RZ/V2N

          - renesas,r9a09g057-sys # RZ/V2H



  reg:

Documentation/devicetree/bindings/soc/renesas/renesas.yaml

+15 −0
Original line number Diff line number Diff line
@@ -551,6 +551,21 @@ properties: 
              - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

          - const: renesas,r9a09g047



      - description: RZ/V2N (R9A09G056)

        items:

          - enum:

              - renesas,rzv2n-evk # RZ/V2N EVK (RTK0EF0186C03000BJ)

          - enum:

              - renesas,r9a09g056n41 # RZ/V2N

              - renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support

              - renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support

              - renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 support

              - renesas,r9a09g056n45 # RZ/V2N with cryptographic extension support

              - renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographic extension support

              - renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographic extension support

              - renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + cryptographic extension support

          - const: renesas,r9a09g056



      - description: RZ/V2H(P) (R9A09G057)

        items:

          - enum:

drivers/clk/renesas/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ config CLK_RENESAS 
	select CLK_R9A08G045 if ARCH_R9A08G045

	select CLK_R9A09G011 if ARCH_R9A09G011

	select CLK_R9A09G047 if ARCH_R9A09G047

	select CLK_R9A09G056 if ARCH_R9A09G056

	select CLK_R9A09G057 if ARCH_R9A09G057

	select CLK_SH73A0 if ARCH_SH73A0
@@ -199,6 +200,10 @@ config CLK_R9A09G047 
       bool "RZ/G3E clock support" if COMPILE_TEST

       select CLK_RZV2H



config CLK_R9A09G056

       bool "RZ/V2N clock support" if COMPILE_TEST

       select CLK_RZV2H



config CLK_R9A09G057

       bool "RZ/V2H(P) clock support" if COMPILE_TEST

       select CLK_RZV2H