Commit befcc893 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2024-10-11' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Weekly fixes haul for drm, lots of small fixes all over, amdgpu, xe
  lead the way, some minor nouveau and radeon fixes, and then a bunch of
  misc all over.

  Nothing too scary or out of the unusual.

  sched:
   - Avoid leaking lockdep map

  fbdev-dma:
   - Only clean up deferred I/O if instanciated

  amdgpu:
   - Fix invalid UBSAN warnings
   - Fix artifacts in MPO transitions
   - Hibernation fix

  amdkfd:
   - Fix an eviction fence leak

  radeon:
   - Add late register for connectors
   - Always set GEM function pointers

  i915:
   - HDCP refcount fix

  nouveau:
   - dmem: Fix privileged error in copy engine channel; Fix possible
     data leak in migrate_to_ram()
   - gsp: Fix coding style

  v3d:
   - Stop active perfmon before destroying it

  vc4:
   - Stop active perfmon before destroying it

  xe:
   - Drop GuC submit_wq pool
   - Fix error checking with xa_store()
   - Fix missing freq restore on GSC load error
   - Fix wedged_mode file permission
   - Fix use-after-free in ct communication"

* tag 'drm-fixes-2024-10-11' of https://gitlab.freedesktop.org/drm/kernel:
  drm/fbdev-dma: Only cleanup deferred I/O if necessary
  drm/xe: Make wedged_mode debugfs writable
  drm/xe: Restore GT freq on GSC load error
  drm/xe/guc_submit: fix xa_store() error checking
  drm/xe/ct: fix xa_store() error checking
  drm/xe/ct: prevent UAF in send_recv()
  drm/radeon: always set GEM function pointer
  nouveau/dmem: Fix vulnerability in migrate_to_ram upon copy error
  nouveau/dmem: Fix privileged error in copy engine channel
  drm/amd/display: fix hibernate entry for DCN35+
  drm/amd/display: Clear update flags after update has been applied
  drm/amdgpu: partially revert powerplay `__counted_by` changes
  drm/radeon: add late_register for connector
  drm/amdkfd: Fix an eviction fence leak
  drm/vc4: Stop the active perfmon before being destroyed
  drm/v3d: Stop the active perfmon before being destroyed
  drm/i915/hdcp: fix connector refcounting
  drm/nouveau/gsp: remove extraneous ; after mutex
  drm/xe: Drop GuC submit_wq pool
  drm/sched: Use drm sched lockdep map for submit_wq
parents 1d227fcc ac44ff7c

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+2 −2
Original line number Diff line number Diff line
@@ -1439,7 +1439,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, 
	list_add_tail(&vm->vm_list_node,

			&(vm->process_info->vm_list_head));

	vm->process_info->n_vms++;



	if (ef)

		*ef = dma_fence_get(&vm->process_info->eviction_fence->base);

	mutex_unlock(&vm->process_info->lock);

drivers/gpu/drm/amd/amdkfd/kfd_process.c

+5 −2
Original line number Diff line number Diff line
@@ -1702,12 +1702,15 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd, 


	ret = amdgpu_amdkfd_gpuvm_acquire_process_vm(dev->adev, avm,

						     &p->kgd_process_info,

						     &ef);

						     p->ef ? NULL : &ef);

	if (ret) {

		dev_err(dev->adev->dev, "Failed to create process VM object\n");

		return ret;

	}



	if (!p->ef)

		RCU_INIT_POINTER(p->ef, ef);



	pdd->drm_priv = drm_file->private_data;



	ret = kfd_process_device_reserve_ib_mem(pdd);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+4 −3
Original line number Diff line number Diff line
@@ -2972,10 +2972,11 @@ static int dm_suspend(void *handle) 


	hpd_rx_irq_work_suspend(dm);



	if (adev->dm.dc->caps.ips_support)

		dc_allow_idle_optimizations(adev->dm.dc, true);



	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);



	if (dm->dc->caps.ips_support && adev->in_s0ix)

		dc_allow_idle_optimizations(dm->dc, true);



	dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);



	return 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

+34 −11
Original line number Diff line number Diff line
@@ -5065,11 +5065,26 @@ static bool update_planes_and_stream_v3(struct dc *dc, 
	return true;

}



static void clear_update_flags(struct dc_surface_update *srf_updates,

	int surface_count, struct dc_stream_state *stream)

{

	int i;



	if (stream)

		stream->update_flags.raw = 0;



	for (i = 0; i < surface_count; i++)

		if (srf_updates[i].surface)

			srf_updates[i].surface->update_flags.raw = 0;

}



bool dc_update_planes_and_stream(struct dc *dc,

		struct dc_surface_update *srf_updates, int surface_count,

		struct dc_stream_state *stream,

		struct dc_stream_update *stream_update)

{

	bool ret = false;



	dc_exit_ips_for_hw_access(dc);

	/*

	 * update planes and stream version 3 separates FULL and FAST updates
@@ -5086,10 +5101,16 @@ bool dc_update_planes_and_stream(struct dc *dc, 
	 * features as they are now transparent to the new sequence.

	 */

	if (dc->ctx->dce_version >= DCN_VERSION_4_01)

		return update_planes_and_stream_v3(dc, srf_updates,

		ret = update_planes_and_stream_v3(dc, srf_updates,

				surface_count, stream, stream_update);

	return update_planes_and_stream_v2(dc, srf_updates,

	else

		ret = update_planes_and_stream_v2(dc, srf_updates,

			surface_count, stream, stream_update);



	if (ret)

		clear_update_flags(srf_updates, surface_count, stream);



	return ret;

}



void dc_commit_updates_for_stream(struct dc *dc,
@@ -5099,6 +5120,8 @@ void dc_commit_updates_for_stream(struct dc *dc, 
		struct dc_stream_update *stream_update,

		struct dc_state *state)

{

	bool ret = false;



	dc_exit_ips_for_hw_access(dc);

	/* TODO: Since change commit sequence can have a huge impact,

	 * we decided to only enable it for DCN3x. However, as soon as
@@ -5106,17 +5129,17 @@ void dc_commit_updates_for_stream(struct dc *dc, 
	 * the new sequence for all ASICs.

	 */

	if (dc->ctx->dce_version >= DCN_VERSION_4_01) {

		update_planes_and_stream_v3(dc, srf_updates, surface_count,

		ret = update_planes_and_stream_v3(dc, srf_updates, surface_count,

				stream, stream_update);

		return;

	}

	if (dc->ctx->dce_version >= DCN_VERSION_3_2) {

		update_planes_and_stream_v2(dc, srf_updates, surface_count,

	} else if (dc->ctx->dce_version >= DCN_VERSION_3_2) {

		ret = update_planes_and_stream_v2(dc, srf_updates, surface_count,

				stream, stream_update);

		return;

	}

	update_planes_and_stream_v1(dc, srf_updates, surface_count, stream,

	} else

		ret = update_planes_and_stream_v1(dc, srf_updates, surface_count, stream,

				stream_update, state);



	if (ret)

		clear_update_flags(srf_updates, surface_count, stream);

}



uint8_t dc_get_current_stream_count(struct dc *dc)

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

+13 −13
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ struct vi_dpm_level { 


struct vi_dpm_table {

	uint32_t count;

	struct vi_dpm_level dpm_level[] __counted_by(count);

	struct vi_dpm_level dpm_level[];

};



#define PCIE_PERF_REQ_REMOVE_REGISTRY   0
@@ -91,7 +91,7 @@ struct phm_set_power_state_input { 


struct phm_clock_array {

	uint32_t count;

	uint32_t values[] __counted_by(count);

	uint32_t values[];

};



struct phm_clock_voltage_dependency_record {
@@ -123,7 +123,7 @@ struct phm_acpclock_voltage_dependency_record { 


struct phm_clock_voltage_dependency_table {

	uint32_t count;

	struct phm_clock_voltage_dependency_record entries[] __counted_by(count);

	struct phm_clock_voltage_dependency_record entries[];

};



struct phm_phase_shedding_limits_record {
@@ -140,7 +140,7 @@ struct phm_uvd_clock_voltage_dependency_record { 


struct phm_uvd_clock_voltage_dependency_table {

	uint8_t count;

	struct phm_uvd_clock_voltage_dependency_record entries[] __counted_by(count);

	struct phm_uvd_clock_voltage_dependency_record entries[];

};



struct phm_acp_clock_voltage_dependency_record {
@@ -150,7 +150,7 @@ struct phm_acp_clock_voltage_dependency_record { 


struct phm_acp_clock_voltage_dependency_table {

	uint32_t count;

	struct phm_acp_clock_voltage_dependency_record entries[] __counted_by(count);

	struct phm_acp_clock_voltage_dependency_record entries[];

};



struct phm_vce_clock_voltage_dependency_record {
@@ -161,32 +161,32 @@ struct phm_vce_clock_voltage_dependency_record { 


struct phm_phase_shedding_limits_table {

	uint32_t count;

	struct phm_phase_shedding_limits_record  entries[] __counted_by(count);

	struct phm_phase_shedding_limits_record  entries[];

};



struct phm_vceclock_voltage_dependency_table {

	uint8_t count;

	struct phm_vceclock_voltage_dependency_record entries[] __counted_by(count);

	struct phm_vceclock_voltage_dependency_record entries[];

};



struct phm_uvdclock_voltage_dependency_table {

	uint8_t count;

	struct phm_uvdclock_voltage_dependency_record entries[] __counted_by(count);

	struct phm_uvdclock_voltage_dependency_record entries[];

};



struct phm_samuclock_voltage_dependency_table {

	uint8_t count;

	struct phm_samuclock_voltage_dependency_record entries[] __counted_by(count);

	struct phm_samuclock_voltage_dependency_record entries[];

};



struct phm_acpclock_voltage_dependency_table {

	uint32_t count;

	struct phm_acpclock_voltage_dependency_record entries[] __counted_by(count);

	struct phm_acpclock_voltage_dependency_record entries[];

};



struct phm_vce_clock_voltage_dependency_table {

	uint8_t count;

	struct phm_vce_clock_voltage_dependency_record entries[] __counted_by(count);

	struct phm_vce_clock_voltage_dependency_record entries[];

};
@@ -393,7 +393,7 @@ union phm_cac_leakage_record { 


struct phm_cac_leakage_table {

	uint32_t count;

	union phm_cac_leakage_record entries[] __counted_by(count);

	union phm_cac_leakage_record entries[];

};



struct phm_samu_clock_voltage_dependency_record {
@@ -404,7 +404,7 @@ struct phm_samu_clock_voltage_dependency_record { 


struct phm_samu_clock_voltage_dependency_table {

	uint8_t count;

	struct phm_samu_clock_voltage_dependency_record entries[] __counted_by(count);

	struct phm_samu_clock_voltage_dependency_record entries[];

};



struct phm_cac_tdp_table {