Unverified Commit bf40c1a5 authored by Ben Zong-You Xie's avatar Ben Zong-You Xie Committed by Arnd Bergmann
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MAINTAINERS: Add entry for Andes SoC 



Add entry for Andes SoC maintainer and related files

Signed-off-by: default avatarBen Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-10-ben717@andestech.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent ad087c91

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -21285,6 +21285,15 @@ F: drivers/irqchip/irq-riscv-intc.c 
F:	include/linux/irqchip/riscv-aplic.h

F:	include/linux/irqchip/riscv-imsic.h









RISC-V ANDES SoC Support









M:	Ben Zong-You Xie <ben717@andestech.com>









S:	Maintained









T:	git: https://github.com/ben717-linux/linux









F:	Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml









F:	Documentation/devicetree/bindings/riscv/andes.yaml









F:	Documentation/devicetree/bindings/timer/andestech,plmt0.yaml









F:	arch/riscv/boot/dts/andes/

















RISC-V ARCHITECTURE









M:	Paul Walmsley <paul.walmsley@sifive.com>









M:	Palmer Dabbelt <palmer@dabbelt.com>