Commit bf51d3b2 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
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clk: renesas: rzg2l: Trust value returned by hardware 



The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b.  The
hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that
setting 0 is prohibited.  Hence rzg2l_cpg_sd_clk_mux_get_parent() should
just read CPG_PL2SDHI_DSEL, trust the value, and return the proper clock
parent index based on the value read.

Fixes: eaff3364 ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-5-claudiu.beznea@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent d2692ed4

drivers/clk/renesas/rzg2l-cpg.c

+1 −7
Original line number Diff line number Diff line
@@ -238,14 +238,8 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) 


	val >>= GET_SHIFT(hwdata->conf);

	val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0);

	if (val) {

		val--;

	} else {

		/* Prohibited clk source, change it to 533 MHz(reset value) */

		rzg2l_cpg_sd_clk_mux_set_parent(hw, 0);

	}



	return val;

	return val ? val - 1 : 0;

}



static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = {