Commit bf6003f2 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Refactor DML2 DC power instance 



[WHY & HOW]
Use a dedicated DC power option and instance pair.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2d2e5472

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

+20 −0
Original line number Diff line number Diff line
@@ -311,6 +311,25 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) 
	dcn401_build_wm_range_table(clk_mgr_base);

}



bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base)

{

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);



	return clk_mgr->smu_present && clk_mgr->dpm_present &&

			((clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels &&

			clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz) ||

			(clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels &&

			clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz) ||

			(clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels &&

			clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz) ||

			(clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels &&

			clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz) ||

			(clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels &&

			clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz) ||

			(clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels &&

			clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz));

}



static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)

{
@@ -1496,6 +1515,7 @@ static struct clk_mgr_funcs dcn401_funcs = { 
		.get_dispclk_from_dentist = dcn401_get_dispclk_from_dentist,

		.get_hard_min_memclk = dcn401_get_hard_min_memclk,

		.get_hard_min_fclk = dcn401_get_hard_min_fclk,

		.is_dc_mode_present = dcn401_is_dc_mode_present,

};



struct clk_mgr_internal *dcn401_clk_mgr_construct(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

+1 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ struct dcn401_clk_mgr { 
};



void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);

bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base);



struct clk_mgr_internal *dcn401_clk_mgr_construct(struct dc_context *ctx,

		struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

+2 −9
Original line number Diff line number Diff line
@@ -194,11 +194,6 @@ static void init_state(struct dc *dc, struct dc_state *state) 
struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params)

{

	struct dc_state *state;

#ifdef CONFIG_DRM_AMD_DC_FP

	struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;



	memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));

#endif



	state = kvzalloc(sizeof(struct dc_state), GFP_KERNEL);
@@ -211,14 +206,12 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p 


#ifdef CONFIG_DRM_AMD_DC_FP

	if (dc->debug.using_dml2) {

		dml2_opt->use_clock_dc_limits = false;

		if (!dml2_create(dc, dml2_opt, &state->bw_ctx.dml2)) {

		if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) {

			dc_state_release(state);

			return NULL;

		}



		dml2_opt->use_clock_dc_limits = true;

		if (!dml2_create(dc, dml2_opt, &state->bw_ctx.dml2_dc_power_source)) {

		if (!dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source)) {

			dc_state_release(state);

			return NULL;

		}

drivers/gpu/drm/amd/display/dc/dc.h

+1 −1
Original line number Diff line number Diff line
@@ -1701,7 +1701,7 @@ struct dc { 
	} scratch;



	struct dml2_configuration_options dml2_options;

	struct dml2_configuration_options dml2_tmp;

	struct dml2_configuration_options dml2_dc_power_options;

	enum dc_acpi_cm_power_state power_state;



};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

+2 −7
Original line number Diff line number Diff line
@@ -145,13 +145,8 @@ void dcn401_init_hw(struct dc *dc) 
		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);



		// mark dcmode limits present if any clock has distinct AC and DC values from SMU

		dc->caps.dcmode_power_limits_present =

				(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dcfclk_mhz) ||

				(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dispclk_mhz) ||

				(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dtbclk_mhz) ||

				(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.fclk_mhz) ||

				(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.memclk_mhz) ||

				(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.socclk_mhz);

		dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present &&

				dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr);

	}



	// Initialize the dccg