Commit bf83dae9 authored by Joey Gouly's avatar Joey Gouly Committed by Will Deacon
Browse files

arm64: enable the Permission Overlay Extension for EL0 



Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to
check if the CPU supports the feature.

Signed-off-by: default avatarJoey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20240822151113.1479789-12-joey.gouly@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 9f82f15d

Documentation/arch/arm64/elf_hwcaps.rst

+2 −0
Original line number Diff line number Diff line
@@ -365,6 +365,8 @@ HWCAP2_SME_SF8DP2 
HWCAP2_SME_SF8DP4

    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.



HWCAP2_POE

    Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -157,6 +157,7 @@ 
#define KERNEL_HWCAP_SME_SF8FMA		__khwcap2_feature(SME_SF8FMA)

#define KERNEL_HWCAP_SME_SF8DP4		__khwcap2_feature(SME_SF8DP4)

#define KERNEL_HWCAP_SME_SF8DP2		__khwcap2_feature(SME_SF8DP2)

#define KERNEL_HWCAP_POE		__khwcap2_feature(POE)



/*

 * This yields a mask that user programs can use to figure out what

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -122,5 +122,6 @@ 
#define HWCAP2_SME_SF8FMA	(1UL << 60)

#define HWCAP2_SME_SF8DP4	(1UL << 61)

#define HWCAP2_SME_SF8DP2	(1UL << 62)

#define HWCAP2_POE		(1UL << 63)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+14 −0
Original line number Diff line number Diff line
@@ -466,6 +466,8 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 
};



static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE),

		       FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),

	ARM64_FTR_END,
@@ -2348,6 +2350,14 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 
	sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);

}



#ifdef CONFIG_ARM64_POE

static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)

{

	sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE);

	sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE);

}

#endif



/* Internal helper functions to match cpu capability type */

static bool

cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
@@ -2876,6 +2886,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.capability = ARM64_HAS_S1POE,

		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,

		.matches = has_cpuid_feature,

		.cpu_enable = cpu_enable_poe,

		ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP)

	},

#endif
@@ -3043,6 +3054,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2),

	HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3),

	HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2),

#ifdef CONFIG_ARM64_POE

	HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE),

#endif

	{},

};

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -143,6 +143,7 @@ static const char *const hwcap_str[] = { 
	[KERNEL_HWCAP_SME_SF8FMA]	= "smesf8fma",

	[KERNEL_HWCAP_SME_SF8DP4]	= "smesf8dp4",

	[KERNEL_HWCAP_SME_SF8DP2]	= "smesf8dp2",

	[KERNEL_HWCAP_POE]		= "poe",

};



#ifdef CONFIG_COMPAT