Commit bf9ca811 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma 

Pull rdma updates from Jason Gunthorpe:
 "Small cycle, with some typical driver updates:

   - General code tidying in siw, hfi1, idrdma, usnic, hns rtrs and
     bnxt_re

   - Many small siw cleanups without an overeaching theme

   - Debugfs stats for hns

   - Fix a TX queue timeout in IPoIB and missed locking of the mcast
     list

   - Support more features of P7 devices in bnxt_re including a new work
     submission protocol

   - CQ interrupts for MANA

   - netlink stats for erdma

   - EFA multipath PCI support

   - Fix Incorrect MR invalidation in iser"

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (66 commits)
  RDMA/bnxt_re: Fix error code in bnxt_re_create_cq()
  RDMA/efa: Add EFA query MR support
  IB/iser: Prevent invalidating wrong MR
  RDMA/erdma: Add hardware statistics support
  RDMA/erdma: Introduce dma pool for hardware responses of CMDQ requests
  IB/iser: iscsi_iser.h: fix kernel-doc warning and spellos
  RDMA/mana_ib: Add CQ interrupt support for RAW QP
  RDMA/mana_ib: query device capabilities
  RDMA/mana_ib: register RDMA device with GDMA
  RDMA/bnxt_re: Fix the sparse warnings
  RDMA/bnxt_re: Fix the offset for GenP7 adapters for user applications
  RDMA/bnxt_re: Share a page to expose per CQ info with userspace
  RDMA/bnxt_re: Add UAPI to share a page with user space
  IB/ipoib: Fix mcast list locking
  RDMA/mlx5: Expose register c0 for RDMA device
  net/mlx5: E-Switch, expose eswitch manager vport
  net/mlx5: Manage ICM type of SW encap
  RDMA/mlx5: Support handling of SW encap ICM area
  net/mlx5: Introduce indirect-sw-encap ICM properties
  RDMA/bnxt_re: Adds MSN table capability for Gen P7 adapters
  ...
parents 141d9c6e d24b923f

drivers/infiniband/hw/bnxt_re/bnxt_re.h

+3 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 
#define __BNXT_RE_H__

#include <rdma/uverbs_ioctl.h>

#include "hw_counters.h"

#include <linux/hashtable.h>

#define ROCE_DRV_MODULE_NAME		"bnxt_re"



#define BNXT_RE_DESC	"Broadcom NetXtreme-C/E RoCE Driver"
@@ -135,6 +136,7 @@ struct bnxt_re_pacing { 
#define BNXT_RE_DB_FIFO_ROOM_SHIFT 15

#define BNXT_RE_GRC_FIFO_REG_BASE 0x2000



#define MAX_CQ_HASH_BITS		(16)

struct bnxt_re_dev {

	struct ib_device		ibdev;

	struct list_head		list;
@@ -189,6 +191,7 @@ struct bnxt_re_dev { 
	struct bnxt_re_pacing pacing;

	struct work_struct dbq_fifo_check_work;

	struct delayed_work dbq_pacing_work;

	DECLARE_HASHTABLE(cq_hash, MAX_CQ_HASH_BITS);

};



#define to_bnxt_re_dev(ptr, member)	\

drivers/infiniband/hw/bnxt_re/hw_counters.c

+2 −2
Original line number Diff line number Diff line
@@ -371,7 +371,7 @@ int bnxt_re_ib_get_hw_stats(struct ib_device *ibdev, 
	}



done:

	return bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?

	return bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?

		BNXT_RE_NUM_EXT_COUNTERS : BNXT_RE_NUM_STD_COUNTERS;

}
@@ -381,7 +381,7 @@ struct rdma_hw_stats *bnxt_re_ib_alloc_hw_port_stats(struct ib_device *ibdev, 
	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);

	int num_counters = 0;



	if (bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))

	if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))

		num_counters = BNXT_RE_NUM_EXT_COUNTERS;

	else

		num_counters = BNXT_RE_NUM_STD_COUNTERS;

drivers/infiniband/hw/bnxt_re/ib_verbs.c

+203 −30
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
#include <rdma/ib_mad.h>

#include <rdma/ib_cache.h>

#include <rdma/uverbs_ioctl.h>

#include <linux/hashtable.h>



#include "bnxt_ulp.h"
@@ -567,6 +568,7 @@ bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset, 
	case BNXT_RE_MMAP_WC_DB:

	case BNXT_RE_MMAP_DBR_BAR:

	case BNXT_RE_MMAP_DBR_PAGE:

	case BNXT_RE_MMAP_TOGGLE_PAGE:

		ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx,

						  &entry->rdma_entry, PAGE_SIZE);

		break;
@@ -1023,7 +1025,7 @@ static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 
	bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);

	/* Consider mapping PSN search memory only for RC QPs. */

	if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {

		psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?

		psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?

						   sizeof(struct sq_psn_search_ext) :

						   sizeof(struct sq_psn_search);

		psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
@@ -1184,7 +1186,8 @@ static struct bnxt_re_qp *bnxt_re_create_shadow_qp 
}



static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,

				struct ib_qp_init_attr *init_attr)

				struct ib_qp_init_attr *init_attr,

				struct bnxt_re_ucontext *uctx)

{

	struct bnxt_qplib_dev_attr *dev_attr;

	struct bnxt_qplib_qp *qplqp;
@@ -1213,7 +1216,7 @@ static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 
		/* Allocate 1 more than what's provided so posting max doesn't

		 * mean empty.

		 */

		entries = roundup_pow_of_two(init_attr->cap.max_recv_wr + 1);

		entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx);

		rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);

		rq->q_full_delta = 0;

		rq->sg_info.pgsize = PAGE_SIZE;
@@ -1233,7 +1236,7 @@ static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 
	qplqp = &qp->qplib_qp;

	dev_attr = &rdev->dev_attr;



	if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {

	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {

		qplqp->rq.max_sge = dev_attr->max_qp_sges;

		if (qplqp->rq.max_sge > dev_attr->max_qp_sges)

			qplqp->rq.max_sge = dev_attr->max_qp_sges;
@@ -1243,7 +1246,7 @@ static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 


static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,

				struct ib_qp_init_attr *init_attr,

				struct ib_udata *udata)

				struct bnxt_re_ucontext *uctx)

{

	struct bnxt_qplib_dev_attr *dev_attr;

	struct bnxt_qplib_qp *qplqp;
@@ -1272,7 +1275,7 @@ static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 
	/* Allocate 128 + 1 more than what's provided */

	diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?

		0 : BNXT_QPLIB_RESERVED_QP_WRS;

	entries = roundup_pow_of_two(entries + diff + 1);

	entries = bnxt_re_init_depth(entries + diff + 1, uctx);

	sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);

	sq->q_full_delta = diff + 1;

	/*
@@ -1288,7 +1291,8 @@ static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 
}



static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,

				       struct ib_qp_init_attr *init_attr)

				       struct ib_qp_init_attr *init_attr,

				       struct bnxt_re_ucontext *uctx)

{

	struct bnxt_qplib_dev_attr *dev_attr;

	struct bnxt_qplib_qp *qplqp;
@@ -1299,8 +1303,8 @@ static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 
	qplqp = &qp->qplib_qp;

	dev_attr = &rdev->dev_attr;



	if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {

		entries = roundup_pow_of_two(init_attr->cap.max_send_wr + 1);

	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {

		entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx);

		qplqp->sq.max_wqe = min_t(u32, entries,

					  dev_attr->max_qp_wqes + 1);

		qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
@@ -1326,7 +1330,7 @@ static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 
		goto out;

	}



	if (bnxt_qplib_is_chip_gen_p5(chip_ctx) &&

	if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) &&

	    init_attr->qp_type == IB_QPT_GSI)

		qptype = CMDQ_CREATE_QP_TYPE_GSI;

out:
@@ -1338,6 +1342,7 @@ static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 
				struct ib_udata *udata)

{

	struct bnxt_qplib_dev_attr *dev_attr;

	struct bnxt_re_ucontext *uctx;

	struct bnxt_qplib_qp *qplqp;

	struct bnxt_re_dev *rdev;

	struct bnxt_re_cq *cq;
@@ -1347,6 +1352,7 @@ static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 
	qplqp = &qp->qplib_qp;

	dev_attr = &rdev->dev_attr;



	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);

	/* Setup misc params */

	ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);

	qplqp->pd = &pd->qplib_pd;
@@ -1388,18 +1394,18 @@ static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 
	}



	/* Setup RQ/SRQ */

	rc = bnxt_re_init_rq_attr(qp, init_attr);

	rc = bnxt_re_init_rq_attr(qp, init_attr, uctx);

	if (rc)

		goto out;

	if (init_attr->qp_type == IB_QPT_GSI)

		bnxt_re_adjust_gsi_rq_attr(qp);



	/* Setup SQ */

	rc = bnxt_re_init_sq_attr(qp, init_attr, udata);

	rc = bnxt_re_init_sq_attr(qp, init_attr, uctx);

	if (rc)

		goto out;

	if (init_attr->qp_type == IB_QPT_GSI)

		bnxt_re_adjust_gsi_sq_attr(qp, init_attr);

		bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx);



	if (udata) /* This will update DPI and qp_handle */

		rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
@@ -1523,7 +1529,7 @@ int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr, 
		goto fail;



	if (qp_init_attr->qp_type == IB_QPT_GSI &&

	    !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) {

	    !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) {

		rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);

		if (rc == -ENODEV)

			goto qp_destroy;
@@ -1715,6 +1721,7 @@ int bnxt_re_create_srq(struct ib_srq *ib_srq, 
{

	struct bnxt_qplib_dev_attr *dev_attr;

	struct bnxt_qplib_nq *nq = NULL;

	struct bnxt_re_ucontext *uctx;

	struct bnxt_re_dev *rdev;

	struct bnxt_re_srq *srq;

	struct bnxt_re_pd *pd;
@@ -1739,13 +1746,14 @@ int bnxt_re_create_srq(struct ib_srq *ib_srq, 
		goto exit;

	}



	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);

	srq->rdev = rdev;

	srq->qplib_srq.pd = &pd->qplib_pd;

	srq->qplib_srq.dpi = &rdev->dpi_privileged;

	/* Allocate 1 more than what's provided so posting max doesn't

	 * mean empty

	 */

	entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);

	entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx);

	if (entries > dev_attr->max_srq_wqes + 1)

		entries = dev_attr->max_srq_wqes + 1;

	srq->qplib_srq.max_wqe = entries;
@@ -2103,6 +2111,9 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 
		qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;

	}

	if (qp_attr_mask & IB_QP_CAP) {

		struct bnxt_re_ucontext *uctx =

			rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);



		qp->qplib_qp.modify_flags |=

				CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |

				CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
@@ -2119,7 +2130,7 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 
				  "Create QP failed - max exceeded");

			return -EINVAL;

		}

		entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);

		entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx);

		qp->qplib_qp.sq.max_wqe = min_t(u32, entries,

						dev_attr->max_qp_wqes + 1);

		qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
@@ -2132,7 +2143,7 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 
		qp->qplib_qp.sq.q_full_delta -= 1;

		qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;

		if (qp->qplib_qp.rq.max_wqe) {

			entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);

			entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx);

			qp->qplib_qp.rq.max_wqe =

				min_t(u32, entries, dev_attr->max_qp_wqes + 1);

			qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
@@ -2900,14 +2911,20 @@ int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 
/* Completion Queues */

int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)

{

	struct bnxt_re_cq *cq;

	struct bnxt_qplib_chip_ctx *cctx;

	struct bnxt_qplib_nq *nq;

	struct bnxt_re_dev *rdev;

	struct bnxt_re_cq *cq;



	cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);

	rdev = cq->rdev;

	nq = cq->qplib_cq.nq;

	cctx = rdev->chip_ctx;



	if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {

		free_page((unsigned long)cq->uctx_cq_page);

		hash_del(&cq->hash_entry);

	}

	bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);

	ib_umem_release(cq->umem);
@@ -2920,13 +2937,16 @@ int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 
int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,

		      struct ib_udata *udata)

{

	struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);

	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);

	struct bnxt_re_ucontext *uctx =

		rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);

	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;

	struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);

	int rc, entries;

	int cqe = attr->cqe;

	struct bnxt_qplib_chip_ctx *cctx;

	struct bnxt_qplib_nq *nq = NULL;

	unsigned int nq_alloc_cnt;

	int cqe = attr->cqe;

	int rc, entries;

	u32 active_cqs;



	if (attr->flags)
@@ -2939,9 +2959,10 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 
	}



	cq->rdev = rdev;

	cctx = rdev->chip_ctx;

	cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);



	entries = roundup_pow_of_two(cqe + 1);

	entries = bnxt_re_init_depth(cqe + 1, uctx);

	if (entries > dev_attr->max_cq_wqes + 1)

		entries = dev_attr->max_cq_wqes + 1;
@@ -2949,8 +2970,6 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 
	cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;

	if (udata) {

		struct bnxt_re_cq_req req;

		struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(

			udata, struct bnxt_re_ucontext, ib_uctx);

		if (ib_copy_from_udata(&req, udata, sizeof(req))) {

			rc = -EFAULT;

			goto fail;
@@ -3002,22 +3021,34 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 
	spin_lock_init(&cq->cq_lock);



	if (udata) {

		struct bnxt_re_cq_resp resp;

		struct bnxt_re_cq_resp resp = {};



		if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {

			hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id);

			/* Allocate a page */

			cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL);

			if (!cq->uctx_cq_page) {

				rc = -ENOMEM;

				goto c2fail;

			}

			resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT;

		}

		resp.cqid = cq->qplib_cq.id;

		resp.tail = cq->qplib_cq.hwq.cons;

		resp.phase = cq->qplib_cq.period;

		resp.rsvd = 0;

		rc = ib_copy_to_udata(udata, &resp, sizeof(resp));

		rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));

		if (rc) {

			ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");

			bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);

			goto c2fail;

			goto free_mem;

		}

	}



	return 0;



free_mem:

	free_page((unsigned long)cq->uctx_cq_page);

c2fail:

	ib_umem_release(cq->umem);

fail:
@@ -3072,12 +3103,11 @@ int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata) 
		return -EINVAL;

	}



	entries = roundup_pow_of_two(cqe + 1);

	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);

	entries = bnxt_re_init_depth(cqe + 1, uctx);

	if (entries > dev_attr->max_cq_wqes + 1)

		entries = dev_attr->max_cq_wqes + 1;



	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext,

					 ib_uctx);

	/* uverbs consumer */

	if (ib_copy_from_udata(&req, udata, sizeof(req))) {

		rc = -EFAULT;
@@ -4108,6 +4138,7 @@ int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 
	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;

	struct bnxt_re_user_mmap_entry *entry;

	struct bnxt_re_uctx_resp resp = {};

	struct bnxt_re_uctx_req ureq = {};

	u32 chip_met_rev_num = 0;

	int rc;
@@ -4157,6 +4188,16 @@ int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 
	if (rdev->pacing.dbr_pacing)

		resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED;



	if (udata->inlen >= sizeof(ureq)) {

		rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)));

		if (rc)

			goto cfail;

		if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) {

			resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;

			uctx->cmask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;

		}

	}



	rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));

	if (rc) {

		ibdev_err(ibdev, "Failed to copy user context");
@@ -4194,6 +4235,19 @@ void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 
	}

}



static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id)

{

	struct bnxt_re_cq *cq = NULL, *tmp_cq;



	hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) {

		if (tmp_cq->qplib_cq.id == cq_id) {

			cq = tmp_cq;

			break;

		}

	}

	return cq;

}



/* Helper function to mmap the virtual memory from user app */

int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)

{
@@ -4235,6 +4289,7 @@ int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 
					rdma_entry);

		break;

	case BNXT_RE_MMAP_DBR_PAGE:

	case BNXT_RE_MMAP_TOGGLE_PAGE:

		/* Driver doesn't expect write access for user space */

		if (vma->vm_flags & VM_WRITE)

			return -EFAULT;
@@ -4411,8 +4466,126 @@ DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV); 
DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV,

			      &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV));



/* Toggle MEM */

static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs)

{

	struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);

	enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE;

	enum bnxt_re_get_toggle_mem_type res_type;

	struct bnxt_re_user_mmap_entry *entry;

	struct bnxt_re_ucontext *uctx;

	struct ib_ucontext *ib_uctx;

	struct bnxt_re_dev *rdev;

	struct bnxt_re_cq *cq;

	u64 mem_offset;

	u64 addr = 0;

	u32 length;

	u32 offset;

	u32 cq_id;

	int err;



	ib_uctx = ib_uverbs_get_ucontext(attrs);

	if (IS_ERR(ib_uctx))

		return PTR_ERR(ib_uctx);



	err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE);

	if (err)

		return err;



	uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);

	rdev = uctx->rdev;



	switch (res_type) {

	case BNXT_RE_CQ_TOGGLE_MEM:

		err = uverbs_copy_from(&cq_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID);

		if (err)

			return err;



		cq = bnxt_re_search_for_cq(rdev, cq_id);

		if (!cq)

			return -EINVAL;



		length = PAGE_SIZE;

		addr = (u64)cq->uctx_cq_page;

		mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE;

		offset = 0;

		break;

	case BNXT_RE_SRQ_TOGGLE_MEM:

		break;



	default:

		return -EOPNOTSUPP;

	}



	entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset);

	if (!entry)

		return -ENOMEM;



	uobj->object = entry;

	uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);

	err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE,

			     &mem_offset, sizeof(mem_offset));

	if (err)

		return err;



	err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,

			     &length, sizeof(length));

	if (err)

		return err;



	err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,

			     &offset, sizeof(length));

	if (err)

		return err;



	return 0;

}



static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject,

				      enum rdma_remove_reason why,

				      struct uverbs_attr_bundle *attrs)

{

	struct  bnxt_re_user_mmap_entry *entry = uobject->object;



	rdma_user_mmap_entry_remove(&entry->rdma_entry);

	return 0;

}



DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM,

			    UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE,

					    BNXT_RE_OBJECT_GET_TOGGLE_MEM,

					    UVERBS_ACCESS_NEW,

					    UA_MANDATORY),

			    UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE,

						 enum bnxt_re_get_toggle_mem_type,

						 UA_MANDATORY),

			    UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID,

					       UVERBS_ATTR_TYPE(u32),

					       UA_MANDATORY),

			    UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE,

						UVERBS_ATTR_TYPE(u64),

						UA_MANDATORY),

			    UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,

						UVERBS_ATTR_TYPE(u32),

						UA_MANDATORY),

			    UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,

						UVERBS_ATTR_TYPE(u32),

						UA_MANDATORY));



DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM,

				    UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE,

						    BNXT_RE_OBJECT_GET_TOGGLE_MEM,

						    UVERBS_ACCESS_DESTROY,

						    UA_MANDATORY));



DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM,

			    UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup),

			    &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM),

			    &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM));



const struct uapi_definition bnxt_re_uapi_defs[] = {

	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE),

	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV),

	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM),

	{}

};

drivers/infiniband/hw/bnxt_re/ib_verbs.h

+10 −0
Original line number Diff line number Diff line
@@ -108,6 +108,8 @@ struct bnxt_re_cq { 
	struct ib_umem		*umem;

	struct ib_umem		*resize_umem;

	int			resize_cqe;

	void			*uctx_cq_page;

	struct hlist_node	hash_entry;

};



struct bnxt_re_mr {
@@ -140,6 +142,7 @@ struct bnxt_re_ucontext { 
	void			*shpg;

	spinlock_t		sh_lock;	/* protect shpg */

	struct rdma_user_mmap_entry *shpage_mmap;

	u64 cmask;

};



enum bnxt_re_mmap_flag {
@@ -148,6 +151,7 @@ enum bnxt_re_mmap_flag { 
	BNXT_RE_MMAP_WC_DB,

	BNXT_RE_MMAP_DBR_PAGE,

	BNXT_RE_MMAP_DBR_BAR,

	BNXT_RE_MMAP_TOGGLE_PAGE,

};



struct bnxt_re_user_mmap_entry {
@@ -167,6 +171,12 @@ static inline u16 bnxt_re_get_rwqe_size(int nsge) 
	return sizeof(struct rq_wqe_hdr) + (nsge * sizeof(struct sq_sge));

}



static inline u32 bnxt_re_init_depth(u32 ent, struct bnxt_re_ucontext *uctx)

{

	return uctx ? (uctx->cmask & BNXT_RE_UCNTX_CMASK_POW2_DISABLED) ?

		ent : roundup_pow_of_two(ent) : ent;

}



int bnxt_re_query_device(struct ib_device *ibdev,

			 struct ib_device_attr *ib_attr,

			 struct ib_udata *udata);

drivers/infiniband/hw/bnxt_re/main.c

+25 −22
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ 
#include <rdma/ib_user_verbs.h>

#include <rdma/ib_umem.h>

#include <rdma/ib_addr.h>

#include <linux/hashtable.h>



#include "bnxt_ulp.h"

#include "roce_hsi.h"
@@ -107,9 +108,14 @@ static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev) 
		dev_info(rdev_to_dev(rdev),

			 "Couldn't get DB bar size, Low latency framework is disabled\n");

	/* set register offsets for both UC and WC */

	if (bnxt_qplib_is_chip_gen_p7(cctx)) {

		res->dpi_tbl.ucreg.offset = offset;

		res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;

	} else {

		res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :

							 BNXT_QPLIB_DBR_PF_DB_OFFSET;

		res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;

	}



	/* If WC mapping is disabled by L2 driver then en_dev->l2_db_size

	 * is equal to the DB-Bar actual size. This indicates that L2
@@ -128,11 +134,13 @@ static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev, u8 mode) 
	struct bnxt_qplib_chip_ctx *cctx;



	cctx = rdev->chip_ctx;

	cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?

	cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?

			       mode : BNXT_QPLIB_WQE_MODE_STATIC;

	if (bnxt_re_hwrm_qcaps(rdev))

		dev_err(rdev_to_dev(rdev),

			"Failed to query hwrm qcaps\n");

	if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx))

		cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT;

}



static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
@@ -215,7 +223,7 @@ static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev) 
	ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,

				attr->max_srq);

	ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq);

	if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))

	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))

		for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)

			rdev->qplib_ctx.tqm_ctx.qcount[i] =

			rdev->dev_attr.tqm_alloc_reqs[i];
@@ -264,7 +272,7 @@ static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev) 
	memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));

	bnxt_re_limit_pf_res(rdev);



	num_vfs =  bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?

	num_vfs =  bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?

			BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs;

	if (num_vfs)

		bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs);
@@ -276,7 +284,7 @@ static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev) 
	if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))

		return;

	rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);

	if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {

	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {

		bnxt_re_set_resource_limits(rdev);

		bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,

					      &rdev->qplib_ctx);
@@ -1203,25 +1211,19 @@ static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq, 
{

	struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,

					     qplib_cq);

	u32 *cq_ptr;



	if (cq->ib_cq.comp_handler) {

		/* Lock comp_handler? */

		if (cq->uctx_cq_page) {

			cq_ptr = (u32 *)cq->uctx_cq_page;

			*cq_ptr = cq->qplib_cq.toggle;

		}

		(*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);

	}



	return 0;

}



#define BNXT_RE_GEN_P5_PF_NQ_DB		0x10000

#define BNXT_RE_GEN_P5_VF_NQ_DB		0x4000

static u32 bnxt_re_get_nqdb_offset(struct bnxt_re_dev *rdev, u16 indx)

{

	return bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?

		(rdev->is_virtfn ? BNXT_RE_GEN_P5_VF_NQ_DB :

				   BNXT_RE_GEN_P5_PF_NQ_DB) :

				   rdev->en_dev->msix_entries[indx].db_offset;

}



static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)

{

	int i;
@@ -1242,7 +1244,7 @@ static int bnxt_re_init_res(struct bnxt_re_dev *rdev) 
	bnxt_qplib_init_res(&rdev->qplib_res);



	for (i = 1; i < rdev->num_msix ; i++) {

		db_offt = bnxt_re_get_nqdb_offset(rdev, i);

		db_offt = rdev->en_dev->msix_entries[i].db_offset;

		rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1],

					  i - 1, rdev->en_dev->msix_entries[i].vector,

					  db_offt, &bnxt_re_cqn_handler,
@@ -1653,7 +1655,7 @@ static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode) 
		ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);

		goto free_rcfw;

	}

	db_offt = bnxt_re_get_nqdb_offset(rdev, BNXT_RE_AEQ_IDX);

	db_offt = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].db_offset;

	vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector;

	rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,

					    vid, db_offt,
@@ -1681,7 +1683,7 @@ static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode) 
	bnxt_re_set_resource_limits(rdev);



	rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0,

				  bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx));

				  bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx));

	if (rc) {

		ibdev_err(&rdev->ibdev,

			  "Failed to allocate QPLIB context: %#x\n", rc);
@@ -1737,6 +1739,7 @@ static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode) 
		 */

		bnxt_re_vf_res_config(rdev);

	}

	hash_init(rdev->cq_hash);



	return 0;

free_sctx:
@@ -1804,7 +1807,7 @@ static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable) 
		return;



	/* Currently enabling only for GenP5 adapters */

	if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))

	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))

		return;



	if (enable) {