Commit bfd9c931 authored by Mark Rutland's avatar Mark Rutland Committed by Will Deacon
Browse files

arm64: tlb: Allow XZR argument to TLBI ops 



The TLBI instruction accepts XZR as a register argument, and for TLBI
operations with a register argument, there is no functional difference
between using XZR or another GPR which contains zeroes. Operations
without a register argument are encoded as if XZR were used.

Allow the __TLBI_1() macro to use XZR when a register argument is all
zeroes.

Today this only results in a trivial code saving in
__do_compat_cache_op()'s workaround for Neoverse-N1 erratum #1542419. In
subsequent patches this pattern will be used more generally.

There should be no functional change as a result of this patch.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oupton@kernel.org>
Cc: Ryan Roberts <ryan.roberts@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 9d1a7c4a

arch/arm64/include/asm/tlbflush.h

+3 −3
Original line number Diff line number Diff line
@@ -38,12 +38,12 @@ 
			    : : )



#define __TLBI_1(op, arg) asm (ARM64_ASM_PREAMBLE			       \

			       "tlbi " #op ", %0\n"			       \

			       "tlbi " #op ", %x0\n"			       \

		   ALTERNATIVE("nop\n			nop",		       \

			       "dsb ish\n		tlbi " #op ", %0",     \

			       "dsb ish\n		tlbi " #op ", %x0",    \

			       ARM64_WORKAROUND_REPEAT_TLBI,		       \

			       CONFIG_ARM64_WORKAROUND_REPEAT_TLBI)	       \

			    : : "r" (arg))

			    : : "rZ" (arg))



#define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg)