Unverified Commit bfe6a264 authored by Jihed Chaibi's avatar Jihed Chaibi Committed by Mark Brown
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ASoC: adau1372: Fix clock leak on PLL lock failure 



adau1372_enable_pll() was a void function that logged a dev_err() on
PLL lock timeout but did not propagate the error. As a result,
adau1372_set_power() would continue with adau1372->enabled set to true
despite the PLL being unlocked, and the mclk left enabled with no
corresponding disable on the error path.

Convert adau1372_enable_pll() to return int, using -ETIMEDOUT on lock
timeout and propagating regmap errors directly. In adau1372_set_power(),
check the return value and unwind in reverse order: restore regcache to
cache-only mode, reassert GPIO power-down, and disable the clock before
returning the error.

Signed-off-by: default avatarJihed Chaibi <jihed.chaibi.dev@gmail.com>
Fixes: 6cd4c645 ("ASoC: Add ADAU1372 audio CODEC support")
Reviewed-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://patch.msgid.link/20260325210704.76847-3-jihed.chaibi.dev@gmail.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 326fe810

sound/soc/codecs/adau1372.c

+14 −3
Original line number Diff line number Diff line
@@ -762,7 +762,7 @@ static int adau1372_startup(struct snd_pcm_substream *substream, struct snd_soc_ 
	return 0;

}



static void adau1372_enable_pll(struct adau1372 *adau1372)

static int adau1372_enable_pll(struct adau1372 *adau1372)

{

	unsigned int val, timeout = 0;

	int ret;
@@ -778,8 +778,12 @@ static void adau1372_enable_pll(struct adau1372 *adau1372) 
		timeout++;

	} while (!(val & 1) && timeout < 3);



	if (ret < 0 || !(val & 1))

	if (ret < 0 || !(val & 1)) {

		dev_err(adau1372->dev, "Failed to lock PLL\n");

		return ret < 0 ? ret : -ETIMEDOUT;

	}



	return 0;

}



static int adau1372_set_power(struct adau1372 *adau1372, bool enable)
@@ -807,7 +811,14 @@ static int adau1372_set_power(struct adau1372 *adau1372, bool enable) 
		 * accessed.

		 */

		if (adau1372->use_pll) {

			adau1372_enable_pll(adau1372);

			ret = adau1372_enable_pll(adau1372);

			if (ret) {

				regcache_cache_only(adau1372->regmap, true);

				if (adau1372->pd_gpio)

					gpiod_set_value(adau1372->pd_gpio, 1);

				clk_disable_unprepare(adau1372->mclk);

				return ret;

			}

			clk_ctrl |= ADAU1372_CLK_CTRL_CLKSRC;

		}