Commit c01e03f9 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom: qmp: move common bits definitions to common header 



Move bit definitions for the common headers to the common phy-qcom-qmp.h
header.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-5-a463d0b57836@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent ef643d55

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+0 −21
Original line number Diff line number Diff line
@@ -41,16 +41,6 @@ 
#include "phy-qcom-qmp-dp-phy-v5.h"

#include "phy-qcom-qmp-dp-phy-v6.h"



/* QPHY_SW_RESET bit */

#define SW_RESET				BIT(0)

/* QPHY_POWER_DOWN_CONTROL */

#define SW_PWRDN				BIT(0)

/* QPHY_START_CONTROL bits */

#define SERDES_START				BIT(0)

#define PCS_START				BIT(1)

/* QPHY_PCS_STATUS bit */

#define PHYSTATUS				BIT(6)



/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */

/* DP PHY soft reset */

#define SW_DPPHY_RESET				BIT(0)
@@ -65,17 +55,6 @@ 
#define USB3_MODE				BIT(0) /* enables USB3 mode */

#define DP_MODE					BIT(1) /* enables DP mode */



/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */

#define ARCVR_DTCT_EN				BIT(0)

#define ALFPS_DTCT_EN				BIT(1)

#define ARCVR_DTCT_EVENT_SEL			BIT(4)



/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */

#define IRQ_CLEAR				BIT(0)



/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */

#define CLAMP_EN				BIT(0) /* enables i/o clamp_n */



/* QPHY_V3_DP_COM_TYPEC_CTRL register bits */

#define SW_PORTSELECT_VAL			BIT(0)

#define SW_PORTSELECT_MUX			BIT(1)

drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c

+1 −9
Original line number Diff line number Diff line
@@ -23,17 +23,9 @@ 


#include "phy-qcom-qmp.h"



/* QPHY_SW_RESET bit */

#define SW_RESET				BIT(0)

/* QPHY_POWER_DOWN_CONTROL */

#define SW_PWRDN				BIT(0)

#define REFCLK_DRV_DSBL				BIT(1)

/* QPHY_START_CONTROL bits */

#define SERDES_START				BIT(0)

#define PCS_START				BIT(1)

#define PLL_READY_GATE_EN			BIT(3)

/* QPHY_PCS_STATUS bit */

#define PHYSTATUS				BIT(6)



/* QPHY_COM_PCS_READY_STATUS bit */

#define PCS_READY				BIT(0)

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+0 −12
Original line number Diff line number Diff line
@@ -34,18 +34,6 @@ 
#include "phy-qcom-qmp-pcs-pcie-v6_20.h"

#include "phy-qcom-qmp-pcie-qhp.h"



/* QPHY_SW_RESET bit */

#define SW_RESET				BIT(0)

/* QPHY_POWER_DOWN_CONTROL */

#define SW_PWRDN				BIT(0)

#define REFCLK_DRV_DSBL				BIT(1)

/* QPHY_START_CONTROL bits */

#define SERDES_START				BIT(0)

#define PCS_START				BIT(1)

/* QPHY_PCS_STATUS bit */

#define PHYSTATUS				BIT(6)

#define PHYSTATUS_4_20				BIT(7)



#define PHY_INIT_COMPLETE_TIMEOUT		10000



/* set of registers with offsets different per-PHY */

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+0 −7
Original line number Diff line number Diff line
@@ -32,13 +32,6 @@ 


#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"



/* QPHY_SW_RESET bit */

#define SW_RESET				BIT(0)

/* QPHY_POWER_DOWN_CONTROL */

#define SW_PWRDN				BIT(0)

/* QPHY_START_CONTROL bits */

#define SERDES_START				BIT(0)

#define PCS_START				BIT(1)

/* QPHY_PCS_READY_STATUS bit */

#define PCS_READY				BIT(0)

drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c

+0 −21
Original line number Diff line number Diff line
@@ -27,16 +27,6 @@ 


#include "phy-qcom-qmp-dp-com-v3.h"



/* QPHY_SW_RESET bit */

#define SW_RESET				BIT(0)

/* QPHY_POWER_DOWN_CONTROL */

#define SW_PWRDN				BIT(0)

/* QPHY_START_CONTROL bits */

#define SERDES_START				BIT(0)

#define PCS_START				BIT(1)

/* QPHY_PCS_STATUS bit */

#define PHYSTATUS				BIT(6)



/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */

/* DP PHY soft reset */

#define SW_DPPHY_RESET				BIT(0)
@@ -51,17 +41,6 @@ 
#define USB3_MODE				BIT(0) /* enables USB3 mode */

#define DP_MODE					BIT(1) /* enables DP mode */



/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */

#define ARCVR_DTCT_EN				BIT(0)

#define ALFPS_DTCT_EN				BIT(1)

#define ARCVR_DTCT_EVENT_SEL			BIT(4)



/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */

#define IRQ_CLEAR				BIT(0)



/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */

#define CLAMP_EN				BIT(0) /* enables i/o clamp_n */



#define PHY_INIT_COMPLETE_TIMEOUT		10000



struct qmp_phy_init_tbl {