Commit c01fba0b authored by Krzysztof Hałasa's avatar Krzysztof Hałasa Committed by Ulf Hansson
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imx8m-blk-ctrl: set ISI panic write hurry level 



Apparently, ISI needs cache settings similar to LCDIF.
Otherwise we get artefacts in the image.
Tested on i.MX8MP.

Signed-off-by: default avatarKrzysztof Hałasa <khalasa@piap.pl>
Link: https://lore.kernel.org/r/m3ldr69lsw.fsf@t19.piap.pl


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 3068b386

drivers/pmdomain/imx/imx8m-blk-ctrl.c

+10 −0
Original line number Diff line number Diff line
@@ -665,6 +665,11 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { 
#define  LCDIF_1_RD_HURRY	GENMASK(15, 13)

#define  LCDIF_0_RD_HURRY	GENMASK(12, 10)



#define ISI_CACHE_CTRL		0x50

#define  ISI_V_WR_HURRY		GENMASK(28, 26)

#define  ISI_U_WR_HURRY		GENMASK(25, 23)

#define  ISI_Y_WR_HURRY		GENMASK(22, 20)



static int imx8mp_media_power_notifier(struct notifier_block *nb,

				unsigned long action, void *data)

{
@@ -694,6 +699,11 @@ static int imx8mp_media_power_notifier(struct notifier_block *nb, 
		regmap_set_bits(bc->regmap, LCDIF_ARCACHE_CTRL,

				FIELD_PREP(LCDIF_1_RD_HURRY, 7) |

				FIELD_PREP(LCDIF_0_RD_HURRY, 7));

		/* Same here for ISI */

		regmap_set_bits(bc->regmap, ISI_CACHE_CTRL,

				FIELD_PREP(ISI_V_WR_HURRY, 7) |

				FIELD_PREP(ISI_U_WR_HURRY, 7) |

				FIELD_PREP(ISI_Y_WR_HURRY, 7));

	}



	return NOTIFY_OK;