Commit c04269c0 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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dt-bindings: clock: renesas: Document RZ/V2N SoC CPG 



Document the device tree bindings for the Renesas RZ/V2N (R9A09G056)
SoC Clock Pulse Generator (CPG).

Update `renesas,rzv2h-cpg.yaml` to include the compatible string for
RZ/V2N SoC and adjust the title and description accordingly.

Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock
constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific
clock driver will be reused for this SoC.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-7-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent dc7af24b

Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

+3 −2
Original line number Diff line number Diff line
@@ -4,13 +4,13 @@ 
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)

title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles

  On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles

  generation and control of clock signals for the IP modules, generation and

  control of resets, and control over booting, low power consumption and power

  supply domains.
@@ -19,6 +19,7 @@ properties: 
  compatible:

    enum:

      - renesas,r9a09g047-cpg # RZ/G3E

      - renesas,r9a09g056-cpg # RZ/V2N

      - renesas,r9a09g057-cpg # RZ/V2H



  reg:

include/dt-bindings/clock/renesas,r9a09g056-cpg.h

0 → 100644
+24 −0
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

 *

 * Copyright (C) 2025 Renesas Electronics Corp.

 */

#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__

#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__



#include <dt-bindings/clock/renesas-cpg-mssr.h>



/* Core Clock list */

#define R9A09G056_SYS_0_PCLK			0

#define R9A09G056_CA55_0_CORE_CLK0		1

#define R9A09G056_CA55_0_CORE_CLK1		2

#define R9A09G056_CA55_0_CORE_CLK2		3

#define R9A09G056_CA55_0_CORE_CLK3		4

#define R9A09G056_CA55_0_PERIPHCLK		5

#define R9A09G056_CM33_CLK0			6

#define R9A09G056_CST_0_SWCLKTCK		7

#define R9A09G056_IOTOP_0_SHCLK			8

#define R9A09G056_USB2_0_CLK_CORE0		9

#define R9A09G056_GBETH_0_CLK_PTP_REF_I		10

#define R9A09G056_GBETH_1_CLK_PTP_REF_I		11



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */