Commit c05d1c40 authored by Kevin Wang's avatar Kevin Wang Committed by Alex Deucher
Browse files

drm/amd/swsmu: add aldebaran smu13 ip support (v3) 



Add initial swSMU support.

v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth)
v2: switch to thm/mp v13_0 ip headers (Hawking)
v3: squash in updates (Alex)

Signed-off-by: default avatarKevin Wang <kevin1.wang@amd.com>
Signed-off-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 465c437a

drivers/gpu/drm/amd/pm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ subdir-ccflags-y += \ 
		-I$(FULL_AMD_PATH)/pm/swsmu \

		-I$(FULL_AMD_PATH)/pm/swsmu/smu11 \

		-I$(FULL_AMD_PATH)/pm/swsmu/smu12 \

		-I$(FULL_AMD_PATH)/pm/swsmu/smu13 \

		-I$(FULL_AMD_PATH)/pm/powerplay \

		-I$(FULL_AMD_PATH)/pm/powerplay/smumgr\

		-I$(FULL_AMD_PATH)/pm/powerplay/hwmgr

drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h

0 → 100644
+109 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef ALDEBARAN_PP_SMC_H

#define ALDEBARAN_PP_SMC_H



#pragma pack(push, 1)



// SMU Response Codes:

#define PPSMC_Result_OK                    0x1

#define PPSMC_Result_Failed                0xFF

#define PPSMC_Result_UnknownCmd            0xFE

#define PPSMC_Result_CmdRejectedPrereq     0xFD

#define PPSMC_Result_CmdRejectedBusy       0xFC



// Message Definitions:

#define PPSMC_MSG_TestMessage                    0x1

#define PPSMC_MSG_GetSmuVersion                  0x2

#define PPSMC_MSG_Mode1Reset                     0x3

#define PPSMC_MSG_GetDriverIfVersion             0x4

#define PPSMC_MSG_spare1                         0x5

#define PPSMC_MSG_spare2                         0x6

#define PPSMC_MSG_EnableAllSmuFeatures           0x7

#define PPSMC_MSG_DisableAllSmuFeatures          0x8

#define PPSMC_MSG_spare3                         0x9

#define PPSMC_MSG_spare4                         0xA

#define PPSMC_MSG_spare5                         0xB

#define PPSMC_MSG_spare6                         0xC

#define PPSMC_MSG_GetEnabledSmuFeaturesLow       0xD

#define PPSMC_MSG_GetEnabledSmuFeaturesHigh      0xE

#define PPSMC_MSG_SetDriverDramAddrHigh          0xF

#define PPSMC_MSG_SetDriverDramAddrLow           0x10

#define PPSMC_MSG_SetToolsDramAddrHigh           0x11

#define PPSMC_MSG_SetToolsDramAddrLow            0x12

#define PPSMC_MSG_TransferTableSmu2Dram          0x13

#define PPSMC_MSG_TransferTableDram2Smu          0x14

#define PPSMC_MSG_UseDefaultPPTable              0x15

#define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x16

#define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x17

#define PPSMC_MSG_SetSoftMinByFreq               0x18

#define PPSMC_MSG_SetSoftMaxByFreq               0x19

#define PPSMC_MSG_SetHardMinByFreq               0x1A

#define PPSMC_MSG_SetHardMaxByFreq               0x1B

#define PPSMC_MSG_GetMinDpmFreq                  0x1C

#define PPSMC_MSG_GetMaxDpmFreq                  0x1D

#define PPSMC_MSG_GetDpmFreqByIndex              0x1E

#define PPSMC_MSG_SetWorkloadMask                0x1F

#define PPSMC_MSG_GetVoltageByDpm                0x20

#define PPSMC_MSG_GetVoltageByDpmOverdrive       0x21

#define PPSMC_MSG_SetPptLimit                    0x22

#define PPSMC_MSG_GetPptLimit                    0x23

#define PPSMC_MSG_PrepareMp1ForUnload            0x24

#define PPSMC_MSG_PrepareMp1ForReset             0x25

#define PPSMC_MSG_SoftReset                      0x26

#define PPSMC_MSG_RunDcBtc                       0x27

#define PPSMC_MSG_DramLogSetDramAddrHigh         0x28

#define PPSMC_MSG_DramLogSetDramAddrLow          0x29

#define PPSMC_MSG_DramLogSetDramSize             0x2A

#define PPSMC_MSG_GetDebugData                   0x2B

#define PPSMC_MSG_WaflTest                       0x2C

#define PPSMC_MSG_spare7                         0x2D

#define PPSMC_MSG_SetMemoryChannelEnable         0x2E

#define PPSMC_MSG_SetNumBadHbmPagesRetired       0x2F

#define PPSMC_MSG_DFCstateControl                0x32

#define PPSMC_MSG_GetGmiPwrDnHyst                0x33

#define PPSMC_MSG_SetGmiPwrDnHyst                0x34

#define PPSMC_MSG_GmiPwrDnControl                0x35

#define PPSMC_MSG_EnterGfxoff                    0x36

#define PPSMC_MSG_ExitGfxoff                     0x37

#define PPSMC_MSG_SetExecuteDMATest              0x38

#define PPSMC_MSG_EnableDeterminism              0x39

#define PPSMC_MSG_DisableDeterminism             0x3A

#define PPSMC_MSG_SetUclkDpmMode                 0x3B



#define PPSMC_Message_Count                      0x3C



typedef enum {

  GFXOFF_ERROR_NO_ERROR,

  GFXOFF_ERROR_DISALLOWED,

  GFXOFF_ERROR_GFX_BUSY,

  GFXOFF_ERROR_GFX_OFF,

  GFXOFF_ERROR_GFX_ON,

} GFXOFF_ERROR_e;



typedef uint32_t PPSMC_Result;

typedef uint32_t PPSMC_Msg;

#pragma pack(pop)



#endif

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

+1 −0
Original line number Diff line number Diff line
@@ -1286,6 +1286,7 @@ extern const struct amd_ip_funcs smu_ip_funcs; 


extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;

extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;

extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;



bool is_support_sw_smu(struct amdgpu_device *adev);

bool is_support_cclk_dpm(struct amdgpu_device *adev);

drivers/gpu/drm/amd/pm/inc/smu_types.h

+23 −4
Original line number Diff line number Diff line
@@ -170,6 +170,13 @@ 
	__SMU_DUMMY_MAP(SetHardMinFclkByFreq),        \

	__SMU_DUMMY_MAP(DFCstateControl), \

	__SMU_DUMMY_MAP(GmiPwrDnControl), \

	__SMU_DUMMY_MAP(spare), \

	__SMU_DUMMY_MAP(SetNumBadHbmPagesRetired), \

	__SMU_DUMMY_MAP(GetGmiPwrDnHyst), \

	__SMU_DUMMY_MAP(SetGmiPwrDnHyst), \

	__SMU_DUMMY_MAP(EnterGfxoff), \

	__SMU_DUMMY_MAP(ExitGfxoff), \

	__SMU_DUMMY_MAP(SetExecuteDMATest), \

	__SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE), \

	__SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \

	__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH), \
@@ -214,6 +221,9 @@ 
       __SMU_DUMMY_MAP(SetSlowPPTLimit),                \

       __SMU_DUMMY_MAP(GetFastPPTLimit),                \

       __SMU_DUMMY_MAP(GetSlowPPTLimit),                \

	__SMU_DUMMY_MAP(EnableDeterminism),		\

	__SMU_DUMMY_MAP(DisableDeterminism),		\

	__SMU_DUMMY_MAP(SetUclkDpmMode),		\



#undef __SMU_DUMMY_MAP

#define __SMU_DUMMY_MAP(type)	SMU_MSG_##type
@@ -239,6 +249,7 @@ enum smu_clk_type { 
	SMU_SCLK,

	SMU_MCLK,

	SMU_PCIE,

	SMU_LCLK,

	SMU_OD_CCLK,

	SMU_OD_SCLK,

	SMU_OD_MCLK,
@@ -255,6 +266,7 @@ enum smu_clk_type { 
       __SMU_DUMMY_MAP(DPM_SOCCLK),                    	\

       __SMU_DUMMY_MAP(DPM_UVD),                       	\

       __SMU_DUMMY_MAP(DPM_VCE),                       	\

       __SMU_DUMMY_MAP(DPM_LCLK),                       \

       __SMU_DUMMY_MAP(ULV),                           	\

       __SMU_DUMMY_MAP(DPM_MP0CLK),                    	\

       __SMU_DUMMY_MAP(DPM_LINK),                      	\
@@ -283,6 +295,7 @@ enum smu_clk_type { 
       __SMU_DUMMY_MAP(DS_MP1CLK),                     	\

       __SMU_DUMMY_MAP(DS_MP0CLK),                     	\

       __SMU_DUMMY_MAP(XGMI),                          	\

       __SMU_DUMMY_MAP(XGMI_PER_LINK_PWR_DWN),          \

       __SMU_DUMMY_MAP(DPM_GFX_PACE),                  	\

       __SMU_DUMMY_MAP(MEM_VDDCI_SCALING),             	\

       __SMU_DUMMY_MAP(MEM_MVDD_SCALING),              	\
@@ -304,6 +317,7 @@ enum smu_clk_type { 
       __SMU_DUMMY_MAP(MMHUB_PG),                      	\

       __SMU_DUMMY_MAP(ATHUB_PG),                      	\

       __SMU_DUMMY_MAP(APCC_DFLL),                     	\

       __SMU_DUMMY_MAP(DF_CSTATE),                     	\

       __SMU_DUMMY_MAP(DPM_GFX_GPO),                    \

       __SMU_DUMMY_MAP(WAFL_CG),                        \

       __SMU_DUMMY_MAP(CCLK_DPM),                     	\
@@ -335,7 +349,12 @@ enum smu_clk_type { 
       __SMU_DUMMY_MAP(ISP_DPM),                        \

       __SMU_DUMMY_MAP(A55_DPM),                        \

       __SMU_DUMMY_MAP(CVIP_DSP_DPM),                   \

       __SMU_DUMMY_MAP(MSMU_LOW_POWER),

       __SMU_DUMMY_MAP(MSMU_LOW_POWER),			\

       __SMU_DUMMY_MAP(FUSE_CG),			\

       __SMU_DUMMY_MAP(MP1_CG),				\

       __SMU_DUMMY_MAP(SMUIO_CG),			\

       __SMU_DUMMY_MAP(THM_CG),				\

       __SMU_DUMMY_MAP(CLK_CG),				\



#undef __SMU_DUMMY_MAP

#define __SMU_DUMMY_MAP(feature)	SMU_FEATURE_##feature##_BIT

drivers/gpu/drm/amd/pm/inc/smu_v13_0.h

0 → 100644
+273 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __SMU_V13_0_H__

#define __SMU_V13_0_H__



#include "amdgpu_smu.h"



#define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF

#define SMU13_DRIVER_IF_VERSION_ALDE 0x5



/* MP Apertures */

#define MP0_Public			0x03800000

#define MP0_SRAM			0x03900000

#define MP1_Public			0x03b00000

#define MP1_SRAM			0x03c00004



/* address block */

#define smnMP1_FIRMWARE_FLAGS		0x3010024

#define smnMP0_FW_INTF			0x30101c0

#define smnMP1_PUB_CTRL			0x3010b14



#define TEMP_RANGE_MIN			(0)

#define TEMP_RANGE_MAX			(80 * 1000)



#define SMU13_TOOL_SIZE			0x19000



#define MAX_DPM_LEVELS 16

#define MAX_PCIE_CONF 2



#define CTF_OFFSET_EDGE			5

#define CTF_OFFSET_HOTSPOT		5

#define CTF_OFFSET_MEM			5



static const struct smu_temperature_range smu13_thermal_policy[] =

{

	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},

	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},

};



struct smu_13_0_max_sustainable_clocks {

	uint32_t display_clock;

	uint32_t phy_clock;

	uint32_t pixel_clock;

	uint32_t uclock;

	uint32_t dcef_clock;

	uint32_t soc_clock;

};



struct smu_13_0_dpm_clk_level {

	bool				enabled;

	uint32_t			value;

};



struct smu_13_0_dpm_table {

	uint32_t			min;        /* MHz */

	uint32_t			max;        /* MHz */

	uint32_t			count;

	struct smu_13_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];

};



struct smu_13_0_pcie_table {

	uint8_t  pcie_gen[MAX_PCIE_CONF];

	uint8_t  pcie_lane[MAX_PCIE_CONF];

};



struct smu_13_0_dpm_tables {

	struct smu_13_0_dpm_table        soc_table;

	struct smu_13_0_dpm_table        gfx_table;

	struct smu_13_0_dpm_table        uclk_table;

	struct smu_13_0_dpm_table        eclk_table;

	struct smu_13_0_dpm_table        vclk_table;

	struct smu_13_0_dpm_table        dclk_table;

	struct smu_13_0_dpm_table        dcef_table;

	struct smu_13_0_dpm_table        pixel_table;

	struct smu_13_0_dpm_table        display_table;

	struct smu_13_0_dpm_table        phy_table;

	struct smu_13_0_dpm_table        fclk_table;

	struct smu_13_0_pcie_table       pcie_table;

};



struct smu_13_0_dpm_context {

	struct smu_13_0_dpm_tables  dpm_tables;

	uint32_t                    workload_policy_mask;

	uint32_t                    dcef_min_ds_clk;

};



enum smu_13_0_power_state {

	SMU_13_0_POWER_STATE__D0 = 0,

	SMU_13_0_POWER_STATE__D1,

	SMU_13_0_POWER_STATE__D3, /* Sleep*/

	SMU_13_0_POWER_STATE__D4, /* Hibernate*/

	SMU_13_0_POWER_STATE__D5, /* Power off*/

};



struct smu_13_0_power_context {

	uint32_t	power_source;

	uint8_t		in_power_limit_boost_mode;

	enum smu_13_0_power_state power_state;

};



enum smu_v13_0_baco_seq {

	BACO_SEQ_BACO = 0,

	BACO_SEQ_MSR,

	BACO_SEQ_BAMACO,

	BACO_SEQ_ULPS,

	BACO_SEQ_COUNT,

};



#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)



int smu_v13_0_init_microcode(struct smu_context *smu);



void smu_v13_0_fini_microcode(struct smu_context *smu);



int smu_v13_0_load_microcode(struct smu_context *smu);



int smu_v13_0_init_smc_tables(struct smu_context *smu);



int smu_v13_0_fini_smc_tables(struct smu_context *smu);



int smu_v13_0_init_power(struct smu_context *smu);



int smu_v13_0_fini_power(struct smu_context *smu);



int smu_v13_0_check_fw_status(struct smu_context *smu);



int smu_v13_0_setup_pptable(struct smu_context *smu);



int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);



int smu_v13_0_check_fw_version(struct smu_context *smu);



int smu_v13_0_set_driver_table_location(struct smu_context *smu);



int smu_v13_0_set_tool_table_location(struct smu_context *smu);



int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);



int smu_v13_0_system_features_control(struct smu_context *smu,

				      bool en);



int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count);



int smu_v13_0_set_allowed_mask(struct smu_context *smu);



int smu_v13_0_notify_display_change(struct smu_context *smu);



int smu_v13_0_get_current_power_limit(struct smu_context *smu,

				      uint32_t *power_limit);



int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n);



int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);



int smu_v13_0_enable_thermal_alert(struct smu_context *smu);



int smu_v13_0_disable_thermal_alert(struct smu_context *smu);



int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);



int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);



int

smu_v13_0_display_clock_voltage_request(struct smu_context *smu,

					struct pp_display_clock_request

					*clock_req);



uint32_t

smu_v13_0_get_fan_control_mode(struct smu_context *smu);



int

smu_v13_0_set_fan_control_mode(struct smu_context *smu,

			       uint32_t mode);



int

smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);



int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,

				uint32_t speed);



int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,

			      uint32_t pstate);



int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);



int smu_v13_0_register_irq_handler(struct smu_context *smu);



int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);



int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,

					       struct pp_smu_nv_clock_table *max_clocks);



bool smu_v13_0_baco_is_support(struct smu_context *smu);



enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);



int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);



int smu_v13_0_baco_enter(struct smu_context *smu);

int smu_v13_0_baco_exit(struct smu_context *smu);



int smu_v13_0_mode1_reset(struct smu_context *smu);



int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

				    uint32_t *min, uint32_t *max);



int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

					  uint32_t min, uint32_t max);



int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,

					  enum smu_clk_type clk_type,

					  uint32_t min,

					  uint32_t max);



int smu_v13_0_set_performance_level(struct smu_context *smu,

				    enum amd_dpm_forced_level level);



int smu_v13_0_set_power_source(struct smu_context *smu,

			       enum smu_power_src_type power_src);



int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,

				    enum smu_clk_type clk_type,

				    uint16_t level,

				    uint32_t *value);



int smu_v13_0_get_dpm_level_count(struct smu_context *smu,

				  enum smu_clk_type clk_type,

				  uint32_t *value);



int smu_v13_0_set_single_dpm_table(struct smu_context *smu,

				   enum smu_clk_type clk_type,

				   struct smu_13_0_dpm_table *single_dpm_table);



int smu_v13_0_get_dpm_level_range(struct smu_context *smu,

				  enum smu_clk_type clk_type,

				  uint32_t *min_value,

				  uint32_t *max_value);



int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);



int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);



int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);



int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);



void smu_v13_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);



int smu_v13_0_gfx_ulv_control(struct smu_context *smu,

			      bool enablement);



#endif

#endif