Commit c064bb5c authored by Hector Martin's avatar Hector Martin Committed by Ulf Hansson
Browse files

mmc: sdhci-pci-gli: GL975[50]: Issue 8/16-bit MMIO reads as 32-bit reads. 



For some reason, <32-bit reads do not work on Apple ARM64 platforms with
these chips (even though they do on other PCIe devices). Issue them as
32-bit reads instead. This is done unconditionally, as it shouldn't hurt
even if not necessary.

Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarHector Martin <marcan@marcan.st>
Link: https://lore.kernel.org/r/20211215161045.38843-3-marcan@marcan.st


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 189f1d9b

drivers/mmc/host/sdhci-pci-gli.c

+23 −0
Original line number Diff line number Diff line
@@ -902,7 +902,28 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 
	return 0;

}



#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)



static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)

{

	u32 val = readl(host->ioaddr + (reg & ~3));

	u16 word;



	word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;

	return word;

}



static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)

{

	u32 val = readl(host->ioaddr + (reg & ~3));

	u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;



	return byte;

}



static const struct sdhci_ops sdhci_gl9755_ops = {

	.read_w			= sdhci_gli_readw,

	.read_b			= sdhci_gli_readb,

	.set_clock		= sdhci_gl9755_set_clock,

	.enable_dma		= sdhci_pci_enable_dma,

	.set_bus_width		= sdhci_set_bus_width,
@@ -922,6 +943,8 @@ const struct sdhci_pci_fixes sdhci_gl9755 = { 
};



static const struct sdhci_ops sdhci_gl9750_ops = {

	.read_w			= sdhci_gli_readw,

	.read_b			= sdhci_gli_readb,

	.read_l                 = sdhci_gl9750_readl,

	.set_clock		= sdhci_gl9750_set_clock,

	.enable_dma		= sdhci_pci_enable_dma,