Commit c06ef68a authored by Austin Zheng's avatar Austin Zheng Committed by Alex Deucher
Browse files

drm/amd/display: Add check for vrr_active_fixed 



Why:
vrr_active_fixed should also be checked when
determining if DRR is in use

How:
Add check for vrr_active_fixed when allow_freesync
and vrr_active_variable are also checked

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarAustin Zheng <austin.zheng@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9aa75e3b

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

+2 −2
Original line number Diff line number Diff line
@@ -554,7 +554,7 @@ static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 
			vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;



	if (vblank_pipe->stream->ignore_msa_timing_param &&

		(vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable))

		(vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed))

		populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);

}
@@ -648,7 +648,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, 
	pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;

	pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;

	pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&

		(subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable);

		(subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed);



	/* Calculate the scaling factor from the src and dst height.

	 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c

+2 −2
Original line number Diff line number Diff line
@@ -706,7 +706,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context) 
				non_subvp_pipes++;

				drr_psr_capable = (drr_psr_capable || dcn32_is_psr_capable(pipe));

				if (pipe->stream->ignore_msa_timing_param &&

						(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable)) {

						(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {

					drr_pipe_found = true;

				}

			}
@@ -764,7 +764,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int 
				non_subvp_pipes++;

				vblank_psr_capable = (vblank_psr_capable || dcn32_is_psr_capable(pipe));

				if (pipe->stream->ignore_msa_timing_param &&

						(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable)) {

						(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {

					drr_pipe_found = true;

				}

			}

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+1 −1
Original line number Diff line number Diff line
@@ -822,7 +822,7 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context) 
			continue;



		if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&

				(drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable))

				(drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable || drr_pipe->stream->vrr_active_fixed))

			break;

	}