Commit c092fc87 authored Apr 05, 2024 by Sean Christopherson

KVM: x86: Inhibit code #DBs in MOV-SS shadow for all Intel compat vCPUs

Treat code #DBs as inhibited in MOV/POP-SS shadows for vCPU models that
are Intel compatible, not just strictly vCPUs with vendor==Intel.  The
behavior is explicitly called out in the SDM, and thus architectural, i.e.
applies to all CPUs that implement Intel's architecture, and isn't a quirk
that is unique to CPUs manufactured by Intel:

  However, if an instruction breakpoint is placed on an instruction located
  immediately after a POP SS/MOV SS instruction, the breakpoint will be
  suppressed as if EFLAGS.RF were 1.

Applying the behavior strictly to Intel wasn't intentional, KVM simply
didn't have a concept of "Intel compatible" as of commit baf67ca8
("KVM: x86: Suppress code #DBs on Intel if MOV/POP SS blocking is active").

Link: https://lore.kernel.org/r/20240405235603.1173076-6-seanjc@google.com


Signed-off-by: Sean Christopherson <seanjc@google.com>

parent 6463e5e4

arch/x86/kvm/x86.c

+6 −8

Original line number	Diff line number	Diff line
		@@ -9028,19 +9028,17 @@ EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);

		static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
		{
		u32 shadow;

		if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
		return true;

		/*
		* Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
		* but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
		* to avoid the relatively expensive CPUID lookup.
		* Intel compatible CPUs inhibit code #DBs when MOV/POP SS blocking is
		* active, but AMD compatible CPUs do not.
		*/
		shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
		return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
		guest_cpuid_is_intel(vcpu);
		if (!guest_cpuid_is_intel_compatible(vcpu))
		return false;

		return static_call(kvm_x86_get_interrupt_shadow)(vcpu) & KVM_X86_SHADOW_INT_MOV_SS;
		}

		static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,