Commit c0c7fa4e authored Jun 10, 2025 by Lorenzo Pieralisi Committed by Will Deacon Jun 12, 2025

docs: arm64: Fix ICC_SRE_EL2 register typo in booting.rst



Fix trivial ICC_SRE_EL2 register spelling typo in booting.rst.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Will Deacon <will@kernel.org>
CC: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250610120935.852034-1-lpieralisi@kernel.org


Signed-off-by: Will Deacon <will@kernel.org>

parent 19272b37

Documentation/arch/arm64/booting.rst

+1 −1

Original line number	Diff line number	Diff line
		@@ -234,7 +234,7 @@ Before jumping into the kernel, the following conditions must be met:

		- If the kernel is entered at EL1:

		- ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
		- ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1
		- ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.

		- The DT or ACPI tables must describe a GICv3 interrupt controller.