Commit c0cfa3a9 authored by Antonio Borneo's avatar Antonio Borneo Committed by Linus Walleij
Browse files

pinctrl: stm32: Support I/O synchronization parameters 



Devices in the stm32mp2xx family include an I/O synchronization
block on each pin that is used to fine tune and improve the I/O
timing margins of high speed synchronous interfaces.
It can be configured to provide independently for each pin:
- skew rate on input direction or latch delay on output direction;
- inversion of clock signals or re-sampling of data signals.

Add support for the generic properties:
- skew-delay-input-ps;
- skew-delay-output-ps.

Add support for the property 'st,io-sync' to configure clock
inversion or data re-sampling mode.

Show the new parameters on debugfs pinconf-pins.

Enable it for the stm32mp257 pinctrl driver.

Co-developed-by: default avatarValentin Caron <valentin.caron@foss.st.com>
Signed-off-by: default avatarValentin Caron <valentin.caron@foss.st.com>
Co-developed-by: default avatarFabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: default avatarFabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: default avatarAntonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 78a3ce94

drivers/pinctrl/stm32/pinctrl-stm32.c

+255 −0
Original line number Diff line number Diff line
@@ -51,9 +51,23 @@ 
#define STM32_GPIO_AFRL		0x20

#define STM32_GPIO_AFRH		0x24

#define STM32_GPIO_SECCFGR	0x30

#define STM32_GPIO_DELAYRL	0x40

#define STM32_GPIO_ADVCFGRL	0x48

#define STM32_GPIO_CIDCFGR(x)	(0x50 + (0x8 * (x)))

#define STM32_GPIO_SEMCR(x)	(0x54 + (0x8 * (x)))



/* Unitary delay for STM32_GPIO_DELAYRL */

#define STM32_GPIO_DELAYRL_PS	250



#define STM32_GPIO_ADVCFGR_DLYPATH_MASK		BIT(0)

#define STM32_GPIO_ADVCFGR_DE_MASK		BIT(1)

#define STM32_GPIO_ADVCFGR_INVCLK_MASK		BIT(2)

#define STM32_GPIO_ADVCFGR_RET_MASK		BIT(3)

#define STM32_GPIO_ADVCFGR_IO_SYNC_MASK		\

	(STM32_GPIO_ADVCFGR_DE_MASK		\

	 | STM32_GPIO_ADVCFGR_INVCLK_MASK	\

	 | STM32_GPIO_ADVCFGR_RET_MASK)



#define STM32_GPIO_CIDCFGR_CFEN		BIT(0)

#define STM32_GPIO_CIDCFGR_SEMEN	BIT(1)

#define STM32_GPIO_CIDCFGR_SCID_MASK	GENMASK(5, 4)
@@ -67,6 +81,9 @@ 


#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)



/* Vendor specific pin configuration */

#define STM32_GPIO_PIN_CONFIG_IO_SYNC	(PIN_CONFIG_END + 1)



#define gpio_range_to_bank(chip) \

		container_of(chip, struct stm32_gpio_bank, range)
@@ -82,6 +99,32 @@ static const char * const stm32_gpio_functions[] = { 
	"reserved",

};



static const char * const stm32_gpio_io_sync[] = {

	"pass-through",

	"clock inverted",

	"data on rising edge",

	"data on falling edge",

	"data on both edges",

};



static u8 io_sync_2_advcfgr[] = {

	/* data or clock GPIO pass-through */

	[0] = 0,

	/* clock GPIO inverted */

	[1] = STM32_GPIO_ADVCFGR_INVCLK_MASK,

	/* data GPIO re-sampled on clock rising edge */

	[2] = STM32_GPIO_ADVCFGR_RET_MASK,

	/* data GPIO re-sampled on clock falling edge */

	[3] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_INVCLK_MASK,

	/* data GPIO re-sampled on both clock edges */

	[4] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_DE_MASK,

};



static const struct pinconf_generic_params stm32_gpio_bindings[] = {

	{"st,io-sync", STM32_GPIO_PIN_CONFIG_IO_SYNC, 0,

	 stm32_gpio_io_sync, ARRAY_SIZE(stm32_gpio_io_sync)},

};



struct stm32_pinctrl_group {

	const char *name;

	unsigned long config;
@@ -95,6 +138,8 @@ struct stm32_pin_backup { 
	unsigned int speed:2;

	unsigned int drive:1;

	unsigned int value:1;

	unsigned int advcfg:4;

	unsigned int skew_delay:4;

};



struct stm32_gpio_bank {
@@ -110,6 +155,7 @@ struct stm32_gpio_bank { 
	struct stm32_pin_backup pin_backup[STM32_GPIO_PINS_PER_BANK];

	u8 irq_type[STM32_GPIO_PINS_PER_BANK];

	bool secure_control;

	bool io_sync_control;

	bool rif_control;

};
@@ -201,6 +247,21 @@ static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, 
	bank->pin_backup[offset].bias = bias;

}



static void stm32_gpio_backup_advcfg(struct stm32_gpio_bank *bank, u32 offset, u32 mask, u32 value)

{

	u32 val;



	val = bank->pin_backup[offset].advcfg;

	val &= ~mask;

	val |= value & mask;

	bank->pin_backup[offset].advcfg = val;

}



static void stm32_gpio_backup_skew_delay(struct stm32_gpio_bank *bank, u32 offset, u32 delay)

{

	bank->pin_backup[offset].skew_delay = delay;

}



/* RIF functions */



static bool stm32_gpio_rif_valid(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
@@ -1145,6 +1206,155 @@ static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 
	return (val >> (offset * 2));

}



static void

stm32_pconf_set_advcfgr_nolock(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)

{

	int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;

	int advcfgr_shift = (offset % 8) * 4;

	u32 val;



	val = readl_relaxed(bank->base + advcfgr_offset);

	val &= ~(mask << advcfgr_shift);

	val |= (value & mask) << advcfgr_shift;

	writel_relaxed(val, bank->base + advcfgr_offset);



	stm32_gpio_backup_advcfg(bank, offset, mask, value);

}



static int stm32_pconf_set_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)

{

	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

	unsigned long flags;

	int err = 0;



	if (!bank->io_sync_control)

		return -ENOTSUPP;



	spin_lock_irqsave(&bank->lock, flags);



	if (pctl->hwlock) {

		err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);

		if (err) {

			dev_err(pctl->dev, "Can't get hwspinlock\n");

			goto unlock;

		}

	}



	stm32_pconf_set_advcfgr_nolock(bank, offset, mask, value);



	if (pctl->hwlock)

		hwspin_unlock_in_atomic(pctl->hwlock);



unlock:

	spin_unlock_irqrestore(&bank->lock, flags);



	return err;

}



static u32 stm32_pconf_get_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask)

{

	int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;

	int advcfgr_shift = (offset % 8) * 4;

	u32 val;



	if (!bank->io_sync_control)

		return 0;



	val = readl_relaxed(bank->base + advcfgr_offset);

	val >>= advcfgr_shift;



	return val & mask;

}



static int stm32_pconf_set_io_sync(struct stm32_gpio_bank *bank, int offset, u32 io_sync)

{

	if (io_sync >= ARRAY_SIZE(io_sync_2_advcfgr))

		return -EINVAL;



	return stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,

		io_sync_2_advcfgr[io_sync]);

}



static const char *stm32_pconf_get_io_sync_str(struct stm32_gpio_bank *bank, int offset)

{

	u32 io_sync = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK);



	if (io_sync & STM32_GPIO_ADVCFGR_RET_MASK) {

		if (io_sync & STM32_GPIO_ADVCFGR_DE_MASK)

			return "data GPIO re-sampled on both clock edges";



		if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK)

			return "data GPIO re-sampled on clock falling edge";



		return "data GPIO re-sampled on clock rising edge";

	}



	if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK)

		return "clock GPIO inverted";



	return NULL;

}



static int

stm32_pconf_set_skew_delay(struct stm32_gpio_bank *bank, int offset, u32 delay, bool is_dir_input)

{

	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

	int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;

	int delay_shift = (offset % 8) * 4;

	unsigned long flags;

	int err = 0;

	u32 val;



	if (!bank->io_sync_control)

		return -ENOTSUPP;



	spin_lock_irqsave(&bank->lock, flags);



	if (pctl->hwlock) {

		err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);

		if (err) {

			dev_err(pctl->dev, "Can't get hwspinlock\n");

			goto unlock;

		}

	}



	val = readl_relaxed(bank->base + delay_offset);

	val &= ~GENMASK(delay_shift + 3, delay_shift);

	val |= (delay << delay_shift);

	writel_relaxed(val, bank->base + delay_offset);



	stm32_gpio_backup_skew_delay(bank, offset, delay);



	stm32_pconf_set_advcfgr_nolock(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK,

				       is_dir_input ? STM32_GPIO_ADVCFGR_DLYPATH_MASK : 0);



	if (pctl->hwlock)

		hwspin_unlock_in_atomic(pctl->hwlock);



unlock:

	spin_unlock_irqrestore(&bank->lock, flags);



	return err;

}



static u32 stm32_pconf_get_skew_delay_val(struct stm32_gpio_bank *bank, int offset)

{

	int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;

	int delay_shift = (offset % 8) * 4;

	u32 val;



	val = readl_relaxed(bank->base + delay_offset);

	val &= GENMASK(delay_shift + 3, delay_shift);



	return val >> delay_shift;

}



static const char *stm32_pconf_get_skew_dir_str(struct stm32_gpio_bank *bank, int offset)

{

	return stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK) ?

		"input" : "output";

}



static bool stm32_pconf_get(struct stm32_gpio_bank *bank,

	unsigned int offset, bool dir)

{
@@ -1207,6 +1417,17 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 
		__stm32_gpio_set(bank, offset, arg);

		ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);

		break;

	case PIN_CONFIG_SKEW_DELAY_INPUT_PS:

		arg /= STM32_GPIO_DELAYRL_PS;

		ret = stm32_pconf_set_skew_delay(bank, offset, arg, true);

		break;

	case PIN_CONFIG_SKEW_DELAY_OUTPUT_PS:

		arg /= STM32_GPIO_DELAYRL_PS;

		ret = stm32_pconf_set_skew_delay(bank, offset, arg, false);

		break;

	case STM32_GPIO_PIN_CONFIG_IO_SYNC:

		ret = stm32_pconf_set_io_sync(bank, offset, arg);

		break;

	default:

		ret = -ENOTSUPP;

	}
@@ -1349,6 +1570,22 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 
	case 3:

		break;

	}



	if (bank->io_sync_control) {

		const char *io_sync_str, *skew_dir_str;

		u32 skew_delay;



		io_sync_str = stm32_pconf_get_io_sync_str(bank, offset);

		skew_dir_str = stm32_pconf_get_skew_dir_str(bank, offset);

		skew_delay = stm32_pconf_get_skew_delay_val(bank, offset);



		if (io_sync_str)

			seq_printf(s, " - IO-sync: %s", io_sync_str);



		if (skew_delay)

			seq_printf(s, " - Skew-delay: %u (%u ps) %s", skew_delay,

				   skew_delay * STM32_GPIO_DELAYRL_PS, skew_dir_str);

	}

}



static const struct pinconf_ops stm32_pconf_ops = {
@@ -1441,6 +1678,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode 
	bank->bank_nr = bank_nr;

	bank->bank_ioport_nr = bank_ioport_nr;

	bank->secure_control = pctl->match_data->secure_control;

	bank->io_sync_control = pctl->match_data->io_sync_control;

	bank->rif_control = pctl->match_data->rif_control;

	spin_lock_init(&bank->lock);
@@ -1683,6 +1921,8 @@ int stm32_pctl_probe(struct platform_device *pdev) 
	pctl->pctl_desc.confops = &stm32_pconf_ops;

	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;

	pctl->pctl_desc.pmxops = &stm32_pmx_ops;

	pctl->pctl_desc.num_custom_params = ARRAY_SIZE(stm32_gpio_bindings);

	pctl->pctl_desc.custom_params = stm32_gpio_bindings;

	pctl->dev = &pdev->dev;



	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
@@ -1804,6 +2044,21 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 
	if (ret)

		return ret;



	if (bank->io_sync_control) {

		bool is_input = bank->pin_backup[offset].advcfg & STM32_GPIO_ADVCFGR_DLYPATH_MASK;



		ret = stm32_pconf_set_skew_delay(bank, offset,

						 bank->pin_backup[offset].skew_delay,

						 is_input);

		if (ret)

			return ret;



		ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,

					      bank->pin_backup[offset].advcfg);

		if (ret)

			return ret;

	}



	if (pin_is_irq)

		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);

drivers/pinctrl/stm32/pinctrl-stm32.h

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ struct stm32_pinctrl_match_data { 
	const struct stm32_desc_pin *pins;

	const unsigned int npins;

	bool secure_control;

	bool io_sync_control;

	bool rif_control;

};

drivers/pinctrl/stm32/pinctrl-stm32mp257.c

+2 −0
Original line number Diff line number Diff line
@@ -2543,6 +2543,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = { 
static struct stm32_pinctrl_match_data stm32mp257_match_data = {

	.pins = stm32mp257_pins,

	.npins = ARRAY_SIZE(stm32mp257_pins),

	.io_sync_control = true,

	.secure_control = true,

	.rif_control = true,

};
@@ -2550,6 +2551,7 @@ static struct stm32_pinctrl_match_data stm32mp257_match_data = { 
static struct stm32_pinctrl_match_data stm32mp257_z_match_data = {

	.pins = stm32mp257_z_pins,

	.npins = ARRAY_SIZE(stm32mp257_z_pins),

	.io_sync_control = true,

	.secure_control = true,

	.rif_control = true,

};