dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX Controller

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip DW HDMI QP TX Encoder

maintainers:

  - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>

description: |

  Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX controller

  IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block, providing the

  following features, among others:

  * Fixed Rate Link (FRL)

  * Display Stream Compression (DSC)

  * 4K@120Hz and 8K@60Hz video modes

  * Variable Refresh Rate (VRR) including Quick Media Switching (QMS)

  * Fast Vactive (FVA)

  * SCDC I2C DDC access

  * Multi-stream audio

  * Enhanced Audio Return Channel (EARC)

allOf:

  - $ref: /schemas/sound/dai-common.yaml#

properties:

  compatible:

    enum:

      - rockchip,rk3588-dw-hdmi-qp

  reg:

    maxItems: 1

  clocks:

    items:

      - description: Peripheral/APB bus clock

      - description: EARC RX biphase clock

      - description: Reference clock

      - description: Audio interface clock

      - description: TMDS/FRL link clock

      - description: Video datapath clock

  clock-names:

    items:

      - const: pclk

      - const: earc

      - const: ref

      - const: aud

      - const: hdp

      - const: hclk_vo1

  interrupts:

    items:

      - description: AVP Unit interrupt

      - description: CEC interrupt

      - description: eARC RX interrupt

      - description: Main Unit interrupt

      - description: HPD interrupt

  interrupt-names:

    items:

      - const: avp

      - const: cec

      - const: earc

      - const: main

      - const: hpd

  phys:

    maxItems: 1

    description: The HDMI/eDP PHY

  ports:

    $ref: /schemas/graph.yaml#/properties/ports

    properties:

      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: Video port for RGB/YUV input.

      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        description: Video port for HDMI/eDP output.

    required:

      - port@0

      - port@1

  power-domains:

    maxItems: 1

  resets:

    maxItems: 2

  reset-names:

    items:

      - const: ref

      - const: hdp

  "#sound-dai-cells":

    const: 0

  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Some HDMI QP related data is accessed through SYS GRF regs.

  rockchip,vo-grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Additional HDMI QP related data is accessed through VO GRF regs.

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - interrupts

  - interrupt-names

  - phys

  - ports

  - resets

  - reset-names

  - rockchip,grf

  - rockchip,vo-grf

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/clock/rockchip,rk3588-cru.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/power/rk3588-power.h>

    #include <dt-bindings/reset/rockchip,rk3588-cru.h>

    soc {

      #address-cells = <2>;

      #size-cells = <2>;

      hdmi@fde80000 {

        compatible = "rockchip,rk3588-dw-hdmi-qp";

        reg = <0x0 0xfde80000 0x0 0x20000>;

        clocks = <&cru PCLK_HDMITX0>,

                 <&cru CLK_HDMITX0_EARC>,

                 <&cru CLK_HDMITX0_REF>,

                 <&cru MCLK_I2S5_8CH_TX>,

                 <&cru CLK_HDMIHDP0>,

                 <&cru HCLK_VO1>;

        clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";

        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;

        interrupt-names = "avp", "cec", "earc", "main", "hpd";

        phys = <&hdptxphy_hdmi0>;

        power-domains = <&power RK3588_PD_VO1>;

        resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;

        reset-names = "ref", "hdp";

        rockchip,grf = <&sys_grf>;

        rockchip,vo-grf = <&vo1_grf>;

        #sound-dai-cells = <0>;

        ports {

          #address-cells = <1>;

          #size-cells = <0>;

          port@0 {

            reg = <0>;

            hdmi0_in_vp0: endpoint {

              remote-endpoint = <&vp0_out_hdmi0>;

            };

          };

          port@1 {

            reg = <1>;

            hdmi0_out_con0: endpoint {

              remote-endpoint = <&hdmi_con0_in>;

            };

          };

        };

      };

    };