Commit c0ecb2a9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-drivers-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull interrupt chip driver updates from Thomas Gleixner:

 - A large refactoring for the Renesas RZV2H driver to add new interrupt
   types cleanly

 - A large refactoring for the Renesas RZG2L driver to add support the
   new RZ/G3L variant

 - Add support for the new NXP S32N79 chip in the IMX irq-steer driver

 - Add support for the Apple AICv3 variant

 - Enhance the Loongson PCH LPC driver so it can be used on MIPS with
   device tree firmware

 - Allow the PIC32 EVIC driver to be built independent of MIPS in
   compile tests

 - The usual small fixes and enhancements all over the place

* tag 'irq-drivers-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (46 commits)
  irqchip/irq-pic32-evic: Add __maybe_unused for board_bind_eic_interrupt in COMPILE_TEST
  irqchip/renesas-rzv2h: Kill icu_err string
  irqchip/renesas-rzv2h: Kill swint_names[]
  irqchip/renesas-rzv2h: Kill swint_idx[]
  irqchip/renesas-rzg2l: Add NMI support
  irqchip/renesas-rzg2l: Clear the shared interrupt bit in rzg2l_irqc_free()
  irqchip/renesas-rzg2l: Replace raw_spin_{lock,unlock} with guard() in rzg2l_irq_set_type()
  irqchip/gic-v3: Print a warning for out-of-range interrupt numbers
  irqchip/renesas-rzg2l: Add shared interrupt support
  irqchip/renesas-rzg2l: Add RZ/G3L support
  irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro
  irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
  irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
  irqchip/renesas-rzg2l: Dynamically allocate fwspec array
  irqchip/renesas-rzg2l: Split rzfive_irqc_{mask,unmask} into separate IRQ and TINT handlers
  irqchip/renesas-rzg2l: Split rzfive_tint_irq_endisable() into separate IRQ and TINT helpers
  irqchip/renesas-rzg2l: Replace rzg2l_irqc_irq_{enable,disable} with TINT-specific handlers
  irqchip/renesas-rzg2l: Split set_type handler into separate IRQ and TINT functions
  irqchip/renesas-rzg2l: Split EOI handler into separate IRQ and TINT functions
  irqchip/renesas-rzg2l: Replace single irq_chip with per-region irq_chip instances
  ...
parents db23954e 1fac04a0

Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml

+21 −9
Original line number Diff line number Diff line
@@ -4,10 +4,10 @@ 
$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Apple Interrupt Controller 2

title: Apple Interrupt Controller 2 and 3



maintainers:

  - Hector Martin <marcan@marcan.st>

  - Janne Grunau <j@jannau.net>



description: |

  The Apple Interrupt Controller 2 is a simple interrupt controller present on
@@ -28,14 +28,24 @@ description: | 
  which do not go through a discrete interrupt controller. It also handles

  FIQ-based Fast IPIs.



  The Apple Interrupt Controller 3 is in its base functionality very similar to

  the Apple Interrupt Controller 2 and uses the same device tree bindings. It is

  found on Apple ARM SoCs platforms starting with t8122 (M3).



properties:

  compatible:

    items:

    oneOf:

      - items:

          - enum:

          - apple,t8112-aic

              - apple,t6000-aic

              - apple,t6020-aic

              - apple,t8112-aic

          - const: apple,aic2

      - items:

          - enum:

              - apple,t6030-aic3

          - const: apple,t8122-aic3

      - const: apple,t8122-aic3



  interrupt-controller: true
@@ -117,7 +127,9 @@ allOf: 
      properties:

        compatible:

          contains:

            const: apple,t8112-aic

            enum:

              - apple,t8112-aic

              - apple,t8122-aic3

    then:

      properties:

        '#interrupt-cells':

Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml

0 → 100644
+52 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Loongson PCH LPC Controller



maintainers:

  - Jiaxun Yang <jiaxun.yang@flygoat.com>



description:

  This interrupt controller is found in the Loongson LS7A family of PCH for

  accepting interrupts sent by LPC-connected peripherals and signalling PIC

  via a single interrupt line when interrupts are available.



properties:

  compatible:

    const: loongson,ls7a-lpc



  reg:

    maxItems: 1



  interrupt-controller: true



  interrupts:

    maxItems: 1



  '#interrupt-cells':

    const: 2



required:

  - compatible

  - reg

  - interrupt-controller

  - interrupts

  - '#interrupt-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    lpc: interrupt-controller@10002000 {

      compatible = "loongson,ls7a-lpc";

      reg = <0x10002000 0x400>;

      interrupt-controller;

      #interrupt-cells = <2>;

      interrupt-parent = <&pic>;

      interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;

    };

...

Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml

+56 −101
Original line number Diff line number Diff line
@@ -30,7 +30,9 @@ properties: 
              - renesas,r9a08g045-irqc     # RZ/G3S

          - const: renesas,rzg2l-irqc



      - const: renesas,r9a07g043f-irqc     # RZ/Five

      - enum:

          - renesas,r9a07g043f-irqc    # RZ/Five

          - renesas,r9a08g046-irqc     # RZ/G3L



  '#interrupt-cells':

    description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
@@ -48,107 +50,35 @@ properties: 


  interrupts:

    minItems: 45

    maxItems: 61



  interrupt-names:

    minItems: 45

    maxItems: 61

    items:

      oneOf:

        - description: NMI interrupt

      - description: IRQ0 interrupt

      - description: IRQ1 interrupt

      - description: IRQ2 interrupt

      - description: IRQ3 interrupt

      - description: IRQ4 interrupt

      - description: IRQ5 interrupt

      - description: IRQ6 interrupt

      - description: IRQ7 interrupt

      - description: GPIO interrupt, TINT0

      - description: GPIO interrupt, TINT1

      - description: GPIO interrupt, TINT2

      - description: GPIO interrupt, TINT3

      - description: GPIO interrupt, TINT4

      - description: GPIO interrupt, TINT5

      - description: GPIO interrupt, TINT6

      - description: GPIO interrupt, TINT7

      - description: GPIO interrupt, TINT8

      - description: GPIO interrupt, TINT9

      - description: GPIO interrupt, TINT10

      - description: GPIO interrupt, TINT11

      - description: GPIO interrupt, TINT12

      - description: GPIO interrupt, TINT13

      - description: GPIO interrupt, TINT14

      - description: GPIO interrupt, TINT15

      - description: GPIO interrupt, TINT16

      - description: GPIO interrupt, TINT17

      - description: GPIO interrupt, TINT18

      - description: GPIO interrupt, TINT19

      - description: GPIO interrupt, TINT20

      - description: GPIO interrupt, TINT21

      - description: GPIO interrupt, TINT22

      - description: GPIO interrupt, TINT23

      - description: GPIO interrupt, TINT24

      - description: GPIO interrupt, TINT25

      - description: GPIO interrupt, TINT26

      - description: GPIO interrupt, TINT27

      - description: GPIO interrupt, TINT28

      - description: GPIO interrupt, TINT29

      - description: GPIO interrupt, TINT30

      - description: GPIO interrupt, TINT31

          const: nmi

        - description: External IRQ interrupt

          pattern: '^irq([0-9]|1[0-5])$'

        - description: GPIO interrupt

          pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$'

        - description: Bus error interrupt

          const: bus-err

        - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt

          const: ec7tie1-0

        - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt

          const: ec7tie2-0

        - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt

          const: ec7tiovf-0

        - description: ECCRAM1 1bit error interrupt

          const: ec7tie1-1

        - description: ECCRAM1 2bit error interrupt

          const: ec7tie2-1

        - description: ECCRAM1 error overflow interrupt



  interrupt-names:

    minItems: 45

    items:

      - const: nmi

      - const: irq0

      - const: irq1

      - const: irq2

      - const: irq3

      - const: irq4

      - const: irq5

      - const: irq6

      - const: irq7

      - const: tint0

      - const: tint1

      - const: tint2

      - const: tint3

      - const: tint4

      - const: tint5

      - const: tint6

      - const: tint7

      - const: tint8

      - const: tint9

      - const: tint10

      - const: tint11

      - const: tint12

      - const: tint13

      - const: tint14

      - const: tint15

      - const: tint16

      - const: tint17

      - const: tint18

      - const: tint19

      - const: tint20

      - const: tint21

      - const: tint22

      - const: tint23

      - const: tint24

      - const: tint25

      - const: tint26

      - const: tint27

      - const: tint28

      - const: tint29

      - const: tint30

      - const: tint31

      - const: bus-err

      - const: ec7tie1-0

      - const: ec7tie2-0

      - const: ec7tiovf-0

      - const: ec7tie1-1

      - const: ec7tie2-1

      - const: ec7tiovf-1

          const: ec7tiovf-1

        - description: Integrated GPT Error interrupt

          pattern: '^ovfunf([0-7])$'



  clocks:

    maxItems: 2
@@ -180,6 +110,24 @@ required: 
allOf:

  - $ref: /schemas/interrupt-controller.yaml#



  - if:

      properties:

        compatible:

          contains:

            enum:

              - renesas,r9a07g043f-irqc

              - renesas,r9a07g043u-irqc

              - renesas,r9a07g044-irqc

              - renesas,r9a07g054-irqc

    then:

      properties:

        interrupts:

          minItems: 48

          maxItems: 48

        interrupt-names:

          minItems: 48

          maxItems: 48



  - if:

      properties:

        compatible:
@@ -192,12 +140,19 @@ allOf: 
          maxItems: 45

        interrupt-names:

          maxItems: 45

    else:



  - if:

      properties:

        compatible:

          contains:

            enum:

              - renesas,r9a08g046-irqc

    then:

      properties:

        interrupts:

          minItems: 48

          minItems: 61

        interrupt-names:

          minItems: 48

          minItems: 61



unevaluatedProperties: false

arch/loongarch/kernel/irq.c

+6 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/irqchip.h>

#include <linux/kernel_stat.h>

#include <linux/proc_fs.h>

#include <linux/minmax.h>

#include <linux/mm.h>

#include <linux/sched.h>

#include <linux/seq_file.h>
@@ -99,6 +100,11 @@ int __init arch_probe_nr_irqs(void) 
	return NR_IRQS_LEGACY;

}



unsigned int arch_dynirq_lower_bound(unsigned int from)

{

	return MAX(from, NR_IRQS_LEGACY);

}



void __init init_IRQ(void)

{

	int i;

arch/mips/loongson64/init.c

+6 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <linux/irqchip.h>

#include <linux/logic_pio.h>

#include <linux/memblock.h>

#include <linux/minmax.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <asm/bootinfo.h>
@@ -227,3 +228,8 @@ void __init arch_init_irq(void) 
	reserve_pio_range();

	irqchip_init();

}



unsigned int arch_dynirq_lower_bound(unsigned int from)

{

	return MAX(from, NR_IRQS_LEGACY);

}