Loading arch/riscv/kvm/main.c +2 −2 Original line number Diff line number Diff line Loading @@ -172,8 +172,8 @@ module_init(riscv_kvm_init); static void __exit riscv_kvm_exit(void) { kvm_riscv_teardown(); kvm_exit(); kvm_riscv_teardown(); } module_exit(riscv_kvm_exit); arch/riscv/kvm/vcpu_onereg.c +1 −1 Original line number Diff line number Diff line Loading @@ -203,7 +203,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_SVADE: /* * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. * Svade is not allowed to disable when the platform use Svade. * Svade can't be disabled unless we support Svadu. */ return arch_has_hw_pte_young(); default: Loading arch/riscv/kvm/vcpu_pmu.c +1 −0 Original line number Diff line number Diff line Loading @@ -666,6 +666,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba .type = etype, .size = sizeof(struct perf_event_attr), .pinned = true, .disabled = true, /* * It should never reach here if the platform doesn't support the sscofpmf * extension as mode filtering won't work without it. Loading tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +56 −25 Original line number Diff line number Diff line Loading @@ -39,7 +39,13 @@ static bool illegal_handler_invoked; #define SBI_PMU_TEST_SNAPSHOT BIT(2) #define SBI_PMU_TEST_OVERFLOW BIT(3) static int disabled_tests; #define SBI_PMU_OVERFLOW_IRQNUM_DEFAULT 5 struct test_args { int disabled_tests; int overflow_irqnum; }; static struct test_args targs; unsigned long pmu_csr_read_num(int csr_num) { Loading Loading @@ -118,8 +124,8 @@ static void stop_counter(unsigned long counter, unsigned long stop_flags) ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, stop_flags, 0, 0, 0); __GUEST_ASSERT(ret.error == 0, "Unable to stop counter %ld error %ld\n", counter, ret.error); __GUEST_ASSERT(ret.error == 0 || ret.error == SBI_ERR_ALREADY_STOPPED, "Unable to stop counter %ld error %ld\n", counter, ret.error); } static void guest_illegal_exception_handler(struct ex_regs *regs) Loading @@ -137,7 +143,6 @@ static void guest_irq_handler(struct ex_regs *regs) unsigned int irq_num = regs->cause & ~CAUSE_IRQ_FLAG; struct riscv_pmu_snapshot_data *snapshot_data = snapshot_gva; unsigned long overflown_mask; unsigned long counter_val = 0; /* Validate that we are in the correct irq handler */ GUEST_ASSERT_EQ(irq_num, IRQ_PMU_OVF); Loading @@ -151,10 +156,6 @@ static void guest_irq_handler(struct ex_regs *regs) GUEST_ASSERT(overflown_mask & 0x01); WRITE_ONCE(vcpu_shared_irq_count, vcpu_shared_irq_count+1); counter_val = READ_ONCE(snapshot_data->ctr_values[0]); /* Now start the counter to mimick the real driver behavior */ start_counter(counter_in_use, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_val); } static unsigned long get_counter_index(unsigned long cbase, unsigned long cmask, Loading Loading @@ -479,7 +480,7 @@ static void test_pmu_events_snaphost(void) static void test_pmu_events_overflow(void) { int num_counters = 0; int num_counters = 0, i = 0; /* Verify presence of SBI PMU and minimum requrired SBI version */ verify_sbi_requirement_assert(); Loading @@ -496,11 +497,15 @@ static void test_pmu_events_overflow(void) * Qemu supports overflow for cycle/instruction. * This test may fail on any platform that do not support overflow for these two events. */ for (i = 0; i < targs.overflow_irqnum; i++) test_pmu_event_overflow(SBI_PMU_HW_CPU_CYCLES); GUEST_ASSERT_EQ(vcpu_shared_irq_count, 1); GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum); vcpu_shared_irq_count = 0; for (i = 0; i < targs.overflow_irqnum; i++) test_pmu_event_overflow(SBI_PMU_HW_INSTRUCTIONS); GUEST_ASSERT_EQ(vcpu_shared_irq_count, 2); GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum); GUEST_DONE(); } Loading Loading @@ -609,7 +614,11 @@ static void test_vm_events_overflow(void *guest_code) vcpu_init_vector_tables(vcpu); /* Initialize guest timer frequency. */ timer_freq = vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency)); /* Export the shared variables to the guest */ sync_global_to_guest(vm, timer_freq); sync_global_to_guest(vm, vcpu_shared_irq_count); sync_global_to_guest(vm, targs); run_vcpu(vcpu); Loading @@ -618,28 +627,38 @@ static void test_vm_events_overflow(void *guest_code) static void test_print_help(char *name) { pr_info("Usage: %s [-h] [-d <test name>]\n", name); pr_info("\t-d: Test to disable. Available tests are 'basic', 'events', 'snapshot', 'overflow'\n"); pr_info("Usage: %s [-h] [-t <test name>] [-n <number of LCOFI interrupt for overflow test>]\n", name); pr_info("\t-t: Test to run (default all). Available tests are 'basic', 'events', 'snapshot', 'overflow'\n"); pr_info("\t-n: Number of LCOFI interrupt to trigger for each event in overflow test (default: %d)\n", SBI_PMU_OVERFLOW_IRQNUM_DEFAULT); pr_info("\t-h: print this help screen\n"); } static bool parse_args(int argc, char *argv[]) { int opt; int temp_disabled_tests = SBI_PMU_TEST_BASIC | SBI_PMU_TEST_EVENTS | SBI_PMU_TEST_SNAPSHOT | SBI_PMU_TEST_OVERFLOW; int overflow_interrupts = 0; while ((opt = getopt(argc, argv, "hd:")) != -1) { while ((opt = getopt(argc, argv, "ht:n:")) != -1) { switch (opt) { case 'd': case 't': if (!strncmp("basic", optarg, 5)) disabled_tests |= SBI_PMU_TEST_BASIC; temp_disabled_tests &= ~SBI_PMU_TEST_BASIC; else if (!strncmp("events", optarg, 6)) disabled_tests |= SBI_PMU_TEST_EVENTS; temp_disabled_tests &= ~SBI_PMU_TEST_EVENTS; else if (!strncmp("snapshot", optarg, 8)) disabled_tests |= SBI_PMU_TEST_SNAPSHOT; temp_disabled_tests &= ~SBI_PMU_TEST_SNAPSHOT; else if (!strncmp("overflow", optarg, 8)) disabled_tests |= SBI_PMU_TEST_OVERFLOW; temp_disabled_tests &= ~SBI_PMU_TEST_OVERFLOW; else goto done; targs.disabled_tests = temp_disabled_tests; break; case 'n': overflow_interrupts = atoi_positive("Number of LCOFI", optarg); break; case 'h': default: Loading @@ -647,6 +666,15 @@ static bool parse_args(int argc, char *argv[]) } } if (overflow_interrupts > 0) { if (targs.disabled_tests & SBI_PMU_TEST_OVERFLOW) { pr_info("-n option is only available for overflow test\n"); goto done; } else { targs.overflow_irqnum = overflow_interrupts; } } return true; done: test_print_help(argv[0]); Loading @@ -655,25 +683,28 @@ static bool parse_args(int argc, char *argv[]) int main(int argc, char *argv[]) { targs.disabled_tests = 0; targs.overflow_irqnum = SBI_PMU_OVERFLOW_IRQNUM_DEFAULT; if (!parse_args(argc, argv)) exit(KSFT_SKIP); if (!(disabled_tests & SBI_PMU_TEST_BASIC)) { if (!(targs.disabled_tests & SBI_PMU_TEST_BASIC)) { test_vm_basic_test(test_pmu_basic_sanity); pr_info("SBI PMU basic test : PASS\n"); } if (!(disabled_tests & SBI_PMU_TEST_EVENTS)) { if (!(targs.disabled_tests & SBI_PMU_TEST_EVENTS)) { test_vm_events_test(test_pmu_events); pr_info("SBI PMU event verification test : PASS\n"); } if (!(disabled_tests & SBI_PMU_TEST_SNAPSHOT)) { if (!(targs.disabled_tests & SBI_PMU_TEST_SNAPSHOT)) { test_vm_events_snapshot_test(test_pmu_events_snaphost); pr_info("SBI PMU event verification with snapshot test : PASS\n"); } if (!(disabled_tests & SBI_PMU_TEST_OVERFLOW)) { if (!(targs.disabled_tests & SBI_PMU_TEST_OVERFLOW)) { test_vm_events_overflow(test_pmu_events_overflow); pr_info("SBI PMU event verification with overflow test : PASS\n"); } Loading Loading
arch/riscv/kvm/main.c +2 −2 Original line number Diff line number Diff line Loading @@ -172,8 +172,8 @@ module_init(riscv_kvm_init); static void __exit riscv_kvm_exit(void) { kvm_riscv_teardown(); kvm_exit(); kvm_riscv_teardown(); } module_exit(riscv_kvm_exit);
arch/riscv/kvm/vcpu_onereg.c +1 −1 Original line number Diff line number Diff line Loading @@ -203,7 +203,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_SVADE: /* * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. * Svade is not allowed to disable when the platform use Svade. * Svade can't be disabled unless we support Svadu. */ return arch_has_hw_pte_young(); default: Loading
arch/riscv/kvm/vcpu_pmu.c +1 −0 Original line number Diff line number Diff line Loading @@ -666,6 +666,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba .type = etype, .size = sizeof(struct perf_event_attr), .pinned = true, .disabled = true, /* * It should never reach here if the platform doesn't support the sscofpmf * extension as mode filtering won't work without it. Loading
tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +56 −25 Original line number Diff line number Diff line Loading @@ -39,7 +39,13 @@ static bool illegal_handler_invoked; #define SBI_PMU_TEST_SNAPSHOT BIT(2) #define SBI_PMU_TEST_OVERFLOW BIT(3) static int disabled_tests; #define SBI_PMU_OVERFLOW_IRQNUM_DEFAULT 5 struct test_args { int disabled_tests; int overflow_irqnum; }; static struct test_args targs; unsigned long pmu_csr_read_num(int csr_num) { Loading Loading @@ -118,8 +124,8 @@ static void stop_counter(unsigned long counter, unsigned long stop_flags) ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, stop_flags, 0, 0, 0); __GUEST_ASSERT(ret.error == 0, "Unable to stop counter %ld error %ld\n", counter, ret.error); __GUEST_ASSERT(ret.error == 0 || ret.error == SBI_ERR_ALREADY_STOPPED, "Unable to stop counter %ld error %ld\n", counter, ret.error); } static void guest_illegal_exception_handler(struct ex_regs *regs) Loading @@ -137,7 +143,6 @@ static void guest_irq_handler(struct ex_regs *regs) unsigned int irq_num = regs->cause & ~CAUSE_IRQ_FLAG; struct riscv_pmu_snapshot_data *snapshot_data = snapshot_gva; unsigned long overflown_mask; unsigned long counter_val = 0; /* Validate that we are in the correct irq handler */ GUEST_ASSERT_EQ(irq_num, IRQ_PMU_OVF); Loading @@ -151,10 +156,6 @@ static void guest_irq_handler(struct ex_regs *regs) GUEST_ASSERT(overflown_mask & 0x01); WRITE_ONCE(vcpu_shared_irq_count, vcpu_shared_irq_count+1); counter_val = READ_ONCE(snapshot_data->ctr_values[0]); /* Now start the counter to mimick the real driver behavior */ start_counter(counter_in_use, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_val); } static unsigned long get_counter_index(unsigned long cbase, unsigned long cmask, Loading Loading @@ -479,7 +480,7 @@ static void test_pmu_events_snaphost(void) static void test_pmu_events_overflow(void) { int num_counters = 0; int num_counters = 0, i = 0; /* Verify presence of SBI PMU and minimum requrired SBI version */ verify_sbi_requirement_assert(); Loading @@ -496,11 +497,15 @@ static void test_pmu_events_overflow(void) * Qemu supports overflow for cycle/instruction. * This test may fail on any platform that do not support overflow for these two events. */ for (i = 0; i < targs.overflow_irqnum; i++) test_pmu_event_overflow(SBI_PMU_HW_CPU_CYCLES); GUEST_ASSERT_EQ(vcpu_shared_irq_count, 1); GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum); vcpu_shared_irq_count = 0; for (i = 0; i < targs.overflow_irqnum; i++) test_pmu_event_overflow(SBI_PMU_HW_INSTRUCTIONS); GUEST_ASSERT_EQ(vcpu_shared_irq_count, 2); GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum); GUEST_DONE(); } Loading Loading @@ -609,7 +614,11 @@ static void test_vm_events_overflow(void *guest_code) vcpu_init_vector_tables(vcpu); /* Initialize guest timer frequency. */ timer_freq = vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency)); /* Export the shared variables to the guest */ sync_global_to_guest(vm, timer_freq); sync_global_to_guest(vm, vcpu_shared_irq_count); sync_global_to_guest(vm, targs); run_vcpu(vcpu); Loading @@ -618,28 +627,38 @@ static void test_vm_events_overflow(void *guest_code) static void test_print_help(char *name) { pr_info("Usage: %s [-h] [-d <test name>]\n", name); pr_info("\t-d: Test to disable. Available tests are 'basic', 'events', 'snapshot', 'overflow'\n"); pr_info("Usage: %s [-h] [-t <test name>] [-n <number of LCOFI interrupt for overflow test>]\n", name); pr_info("\t-t: Test to run (default all). Available tests are 'basic', 'events', 'snapshot', 'overflow'\n"); pr_info("\t-n: Number of LCOFI interrupt to trigger for each event in overflow test (default: %d)\n", SBI_PMU_OVERFLOW_IRQNUM_DEFAULT); pr_info("\t-h: print this help screen\n"); } static bool parse_args(int argc, char *argv[]) { int opt; int temp_disabled_tests = SBI_PMU_TEST_BASIC | SBI_PMU_TEST_EVENTS | SBI_PMU_TEST_SNAPSHOT | SBI_PMU_TEST_OVERFLOW; int overflow_interrupts = 0; while ((opt = getopt(argc, argv, "hd:")) != -1) { while ((opt = getopt(argc, argv, "ht:n:")) != -1) { switch (opt) { case 'd': case 't': if (!strncmp("basic", optarg, 5)) disabled_tests |= SBI_PMU_TEST_BASIC; temp_disabled_tests &= ~SBI_PMU_TEST_BASIC; else if (!strncmp("events", optarg, 6)) disabled_tests |= SBI_PMU_TEST_EVENTS; temp_disabled_tests &= ~SBI_PMU_TEST_EVENTS; else if (!strncmp("snapshot", optarg, 8)) disabled_tests |= SBI_PMU_TEST_SNAPSHOT; temp_disabled_tests &= ~SBI_PMU_TEST_SNAPSHOT; else if (!strncmp("overflow", optarg, 8)) disabled_tests |= SBI_PMU_TEST_OVERFLOW; temp_disabled_tests &= ~SBI_PMU_TEST_OVERFLOW; else goto done; targs.disabled_tests = temp_disabled_tests; break; case 'n': overflow_interrupts = atoi_positive("Number of LCOFI", optarg); break; case 'h': default: Loading @@ -647,6 +666,15 @@ static bool parse_args(int argc, char *argv[]) } } if (overflow_interrupts > 0) { if (targs.disabled_tests & SBI_PMU_TEST_OVERFLOW) { pr_info("-n option is only available for overflow test\n"); goto done; } else { targs.overflow_irqnum = overflow_interrupts; } } return true; done: test_print_help(argv[0]); Loading @@ -655,25 +683,28 @@ static bool parse_args(int argc, char *argv[]) int main(int argc, char *argv[]) { targs.disabled_tests = 0; targs.overflow_irqnum = SBI_PMU_OVERFLOW_IRQNUM_DEFAULT; if (!parse_args(argc, argv)) exit(KSFT_SKIP); if (!(disabled_tests & SBI_PMU_TEST_BASIC)) { if (!(targs.disabled_tests & SBI_PMU_TEST_BASIC)) { test_vm_basic_test(test_pmu_basic_sanity); pr_info("SBI PMU basic test : PASS\n"); } if (!(disabled_tests & SBI_PMU_TEST_EVENTS)) { if (!(targs.disabled_tests & SBI_PMU_TEST_EVENTS)) { test_vm_events_test(test_pmu_events); pr_info("SBI PMU event verification test : PASS\n"); } if (!(disabled_tests & SBI_PMU_TEST_SNAPSHOT)) { if (!(targs.disabled_tests & SBI_PMU_TEST_SNAPSHOT)) { test_vm_events_snapshot_test(test_pmu_events_snaphost); pr_info("SBI PMU event verification with snapshot test : PASS\n"); } if (!(disabled_tests & SBI_PMU_TEST_OVERFLOW)) { if (!(targs.disabled_tests & SBI_PMU_TEST_OVERFLOW)) { test_vm_events_overflow(test_pmu_events_overflow); pr_info("SBI PMU event verification with overflow test : PASS\n"); } Loading