Commit c0fef45d authored by Jiri Slaby (SUSE)'s avatar Jiri Slaby (SUSE) Committed by Greg Kroah-Hartman
Browse files

char/mwave: drop it 



When I tried to clean up the driver a bit, Arnd noted:
> According to thinkwiki.de, the 3780i modem was only used in a
> couple of Thinkpad models that are now over 25 years old, using
> Pentium II processors, and they all have a physical RS232 port
> that can be used to connect an external modem instead.
>
> Maybe we can just retire this driver?

So instead of the clean up, drop the driver altogether.

Signed-off-by: default avatarJiri Slaby (SUSE) <jirislaby@kernel.org>
Suggested-by: default avatarArnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/all/b8834e5d-fdde-4b1a-8757-288dddc507a9@app.fastmail.com/
Link: https://patch.msgid.link/20251124103952.995229-1-jirislaby@kernel.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 1f4c9d8a

Documentation/admin-guide/devices.txt

+1 −1
Original line number Diff line number Diff line
@@ -352,7 +352,7 @@ 
		216 = /dev/fujitsu/apanel	Fujitsu/Siemens application panel

		217 = /dev/ni/natmotn		National Instruments Motion

		218 = /dev/kchuid	Inter-process chuid control

		219 = /dev/modems/mwave	MWave modem firmware upload

		219 =

		220 = /dev/mptctl	Message passing technology (MPT) control

		221 = /dev/mvista/hssdsi	Montavista PICMG hot swap system driver

		222 = /dev/mvista/hasi		Montavista PICMG high availability

Documentation/userspace-api/ioctl/ioctl-number.rst

+0 −1
Original line number Diff line number Diff line
@@ -397,7 +397,6 @@ Code Seq# Include File Comments 
0xCD  01     linux/reiserfs_fs.h                                       Dead since 6.13

0xCE  01-02  uapi/linux/cxl_mem.h                                      Compute Express Link Memory Devices

0xCF  02     fs/smb/client/cifs_ioctl.h

0xDB  00-0F  drivers/char/mwave/mwavepub.h

0xDD  00-3F                                                            ZFCP device driver see drivers/s390/scsi/

                                                                       <mailto:aherrman@de.ibm.com>

0xE5  00-3F  linux/fuse.h

drivers/char/Kconfig

+0 −26
Original line number Diff line number Diff line
@@ -249,32 +249,6 @@ config SONYPI 
	  To compile this driver as a module, choose M here: the

	  module will be called sonypi.



config MWAVE

	tristate "ACP Modem (Mwave) support"

	depends on X86 && TTY

	select SERIAL_8250

	help

	  The ACP modem (Mwave) for Linux is a WinModem. It is composed of a

	  kernel driver and a user level application. Together these components

	  support direct attachment to public switched telephone networks (PSTNs)

	  and support selected world wide countries.



	  This version of the ACP Modem driver supports the IBM Thinkpad 600E,

	  600, and 770 that include on board ACP modem hardware.



	  The modem also supports the standard communications port interface

	  (ttySx) and is compatible with the Hayes AT Command Set.



	  The user level application needed to use this driver can be found at

	  the IBM Linux Technology Center (LTC) web site:

	  <http://www.ibm.com/linux/ltc/>.



	  If you own one of the above IBM Thinkpads which has the Mwave chipset

	  in it, say Y.



	  To compile this driver as a module, choose M here: the

	  module will be called mwave.



config SCx200_GPIO

	tristate "NatSemi SCx200 GPIO Support"

	depends on SCx200

drivers/char/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o 
obj-$(CONFIG_NSC_GPIO)		+= nsc_gpio.o

obj-$(CONFIG_TELCLOCK)		+= tlclk.o



obj-$(CONFIG_MWAVE)		+= mwave/

obj-y				+= agp/



obj-$(CONFIG_HANGCHECK_TIMER)	+= hangcheck-timer.o

drivers/char/mwave/3780i.c

deleted100644 → 0
+0 −536
Original line number Diff line number Diff line 
/*

*

* 3780i.c -- helper routines for the 3780i DSP

*

*

* Written By: Mike Sullivan IBM Corporation

*

* Copyright (C) 1999 IBM Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

* the Free Software Foundation; either version 2 of the License, or

* (at your option) any later version.

*

* This program is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

* GNU General Public License for more details.

*

* NO WARRANTY

* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR

* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT

* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,

* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is

* solely responsible for determining the appropriateness of using and

* distributing the Program and assumes all risks associated with its

* exercise of rights under this Agreement, including but not limited to

* the risks and costs of program errors, damage to or loss of data,

* programs or equipment, and unavailability or interruption of operations.

*

* DISCLAIMER OF LIABILITY

* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY

* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND

* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR

* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE

* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED

* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES

*

* You should have received a copy of the GNU General Public License

* along with this program; if not, write to the Free Software

* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

*

*

* 10/23/2000 - Alpha Release

*	First release to the public

*/



#define pr_fmt(fmt) "3780i: " fmt



#include <linux/kernel.h>

#include <linux/unistd.h>

#include <linux/delay.h>

#include <linux/ioport.h>

#include <linux/bitops.h>

#include <linux/sched.h>	/* cond_resched() */



#include <asm/io.h>

#include <linux/uaccess.h>

#include <asm/irq.h>

#include "smapi.h"

#include "mwavedd.h"

#include "3780i.h"



static DEFINE_SPINLOCK(dsp_lock);



static void PaceMsaAccess(unsigned short usDspBaseIO)

{

	cond_resched();

	udelay(100);

	cond_resched();

}



unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,

                                   unsigned long ulMsaAddr)

{

	unsigned long flags;

	unsigned short val;



	spin_lock_irqsave(&dsp_lock, flags);

	OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);

	OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));

	val = InWordDsp(DSP_MsaDataDSISHigh);

	spin_unlock_irqrestore(&dsp_lock, flags);



	return val;

}



void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,

                          unsigned long ulMsaAddr, unsigned short usValue)

{

	unsigned long flags;



	spin_lock_irqsave(&dsp_lock, flags);

	OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);

	OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));

	OutWordDsp(DSP_MsaDataDSISHigh, usValue);

	spin_unlock_irqrestore(&dsp_lock, flags);

}



static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex,

				 unsigned char ucValue)

{

	DSP_ISA_SLAVE_CONTROL rSlaveControl;

	DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;



	MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);



	rSlaveControl_Save = rSlaveControl;

	rSlaveControl.ConfigMode = true;



	OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));

	OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);

	OutByteDsp(DSP_ConfigData, ucValue);

	OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));

}



int dsp3780I_EnableDSP(struct dsp_3780i_config_settings *pSettings,

                       unsigned short *pIrqMap,

                       unsigned short *pDmaMap)

{

	unsigned long flags;

	unsigned short usDspBaseIO = pSettings->usDspBaseIO;

	int i;

	DSP_UART_CFG_1 rUartCfg1;

	DSP_UART_CFG_2 rUartCfg2;

	DSP_HBRIDGE_CFG_1 rHBridgeCfg1;

	DSP_HBRIDGE_CFG_2 rHBridgeCfg2;

	DSP_BUSMASTER_CFG_1 rBusmasterCfg1;

	DSP_BUSMASTER_CFG_2 rBusmasterCfg2;

	DSP_ISA_PROT_CFG rIsaProtCfg;

	DSP_POWER_MGMT_CFG rPowerMgmtCfg;

	DSP_HBUS_TIMER_CFG rHBusTimerCfg;

	DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable;

	DSP_CHIP_RESET rChipReset;

	DSP_CLOCK_CONTROL_1 rClockControl1;

	DSP_CLOCK_CONTROL_2 rClockControl2;

	DSP_ISA_SLAVE_CONTROL rSlaveControl;

	DSP_HBRIDGE_CONTROL rHBridgeControl;

	unsigned short tval;



	if (!pSettings->bDSPEnabled) {

		pr_err("%s: Error: DSP not enabled. Aborting.\n", __func__);

		return -EIO;

	}



	if (pSettings->bModemEnabled) {

		rUartCfg1.Reserved = rUartCfg2.Reserved = 0;

		rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow;

		rUartCfg1.IrqPulse = pSettings->bUartIrqPulse;

		rUartCfg1.Irq =

			(unsigned char) pIrqMap[pSettings->usUartIrq];

		switch (pSettings->usUartBaseIO) {

		case 0x03F8:

			rUartCfg1.BaseIO = 0;

			break;

		case 0x02F8:

			rUartCfg1.BaseIO = 1;

			break;

		case 0x03E8:

			rUartCfg1.BaseIO = 2;

			break;

		case 0x02E8:

			rUartCfg1.BaseIO = 3;

			break;

		}

		rUartCfg2.Enable = true;

	}



	rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0;

	rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow;

	rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse;

	rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq];

	rHBridgeCfg1.AccessMode = 1;

	rHBridgeCfg2.Enable = true;





	rBusmasterCfg2.Reserved = 0;

	rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma];

	rBusmasterCfg1.NumTransfers =

		(unsigned char) pSettings->usNumTransfers;

	rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest;

	rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16;

	rBusmasterCfg2.IsaMemCmdWidth =

		(unsigned char) pSettings->usIsaMemCmdWidth;





	rIsaProtCfg.Reserved = 0;

	rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY;



	rPowerMgmtCfg.Reserved = 0;

	rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt;



	rHBusTimerCfg.LoadValue =

		(unsigned char) pSettings->usHBusTimerLoadValue;



	rLBusTimeoutDisable.Reserved = 0;

	rLBusTimeoutDisable.DisableTimeout =

		pSettings->bDisableLBusTimeout;



	MKWORD(rChipReset) = ~pSettings->usChipletEnable;



	rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0;

	rClockControl1.N_Divisor = pSettings->usN_Divisor;

	rClockControl1.M_Multiplier = pSettings->usM_Multiplier;



	rClockControl2.Reserved = 0;

	rClockControl2.PllBypass = pSettings->bPllBypass;



	/* Issue a soft reset to the chip */

	/* Note: Since we may be coming in with 3780i clocks suspended, we must keep

	* soft-reset active for 10ms.

	*/

	rSlaveControl.ClockControl = 0;

	rSlaveControl.SoftReset = true;

	rSlaveControl.ConfigMode = false;

	rSlaveControl.Reserved = 0;



	spin_lock_irqsave(&dsp_lock, flags);

	OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));

	MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);



	for (i = 0; i < 11; i++)

		udelay(2000);



	rSlaveControl.SoftReset = false;

	OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));



	MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);



	/* Program our general configuration registers */

	WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1));

	WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2));

	WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1));

	WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2));

	WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg));

	WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg));

	WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg));



	if (pSettings->bModemEnabled) {

		WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1));

		WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2));

	}





	rHBridgeControl.EnableDspInt = false;

	rHBridgeControl.MemAutoInc = true;

	rHBridgeControl.IoAutoInc = false;

	rHBridgeControl.DiagnosticMode = false;



	OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));

	spin_unlock_irqrestore(&dsp_lock, flags);

	WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable));

	WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1));

	WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2));

	WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset));



	ReadMsaCfg(DSP_ChipID);



	return 0;

}



int dsp3780I_DisableDSP(struct dsp_3780i_config_settings *pSettings)

{

	unsigned long flags;

	unsigned short usDspBaseIO = pSettings->usDspBaseIO;

	DSP_ISA_SLAVE_CONTROL rSlaveControl;



	rSlaveControl.ClockControl = 0;

	rSlaveControl.SoftReset = true;

	rSlaveControl.ConfigMode = false;

	rSlaveControl.Reserved = 0;

	spin_lock_irqsave(&dsp_lock, flags);

	OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));



	udelay(5);



	rSlaveControl.ClockControl = 1;

	OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));

	spin_unlock_irqrestore(&dsp_lock, flags);



	udelay(5);



	return 0;

}



int dsp3780I_Reset(struct dsp_3780i_config_settings *pSettings)

{

	unsigned long flags;

	unsigned short usDspBaseIO = pSettings->usDspBaseIO;

	DSP_BOOT_DOMAIN rBootDomain;

	DSP_HBRIDGE_CONTROL rHBridgeControl;



	spin_lock_irqsave(&dsp_lock, flags);

	/* Mask DSP to PC interrupt */

	MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);



	rHBridgeControl.EnableDspInt = false;

	OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));

	spin_unlock_irqrestore(&dsp_lock, flags);



	/* Reset the core via the boot domain register */

	rBootDomain.ResetCore = true;

	rBootDomain.Halt = true;

	rBootDomain.NMI = true;

	rBootDomain.Reserved = 0;



	WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));



	/* Reset all the chiplets and then reactivate them */

	WriteMsaCfg(DSP_ChipReset, 0xFFFF);

	udelay(5);

	WriteMsaCfg(DSP_ChipReset,

			(unsigned short) (~pSettings->usChipletEnable));



	return 0;

}





int dsp3780I_Run(struct dsp_3780i_config_settings *pSettings)

{

	unsigned long flags;

	unsigned short usDspBaseIO = pSettings->usDspBaseIO;

	DSP_BOOT_DOMAIN rBootDomain;

	DSP_HBRIDGE_CONTROL rHBridgeControl;



	/* Transition the core to a running state */

	rBootDomain.ResetCore = true;

	rBootDomain.Halt = false;

	rBootDomain.NMI = true;

	rBootDomain.Reserved = 0;

	WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));



	udelay(5);



	rBootDomain.ResetCore = false;

	WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));

	udelay(5);



	rBootDomain.NMI = false;

	WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));

	udelay(5);



	/* Enable DSP to PC interrupt */

	spin_lock_irqsave(&dsp_lock, flags);

	MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);

	rHBridgeControl.EnableDspInt = true;



	OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));

	spin_unlock_irqrestore(&dsp_lock, flags);



	return 0;

}





int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,

                        unsigned uCount, unsigned long ulDSPAddr)

{

	unsigned long flags;

	unsigned short __user *pusBuffer = pvBuffer;

	unsigned short val;



	/* Set the initial MSA address. No adjustments need to be made to data store addresses */

	spin_lock_irqsave(&dsp_lock, flags);

	OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);

	OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));

	spin_unlock_irqrestore(&dsp_lock, flags);



	/* Transfer the memory block */

	while (uCount-- != 0) {

		spin_lock_irqsave(&dsp_lock, flags);

		val = InWordDsp(DSP_MsaDataDSISHigh);

		spin_unlock_irqrestore(&dsp_lock, flags);

		if(put_user(val, pusBuffer++))

			return -EFAULT;



		PaceMsaAccess(usDspBaseIO);

	}



	return 0;

}



int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,

                                void __user *pvBuffer, unsigned uCount,

                                unsigned long ulDSPAddr)

{

	unsigned long flags;

	unsigned short __user *pusBuffer = pvBuffer;

	unsigned short val;



	/* Set the initial MSA address. No adjustments need to be made to data store addresses */

	spin_lock_irqsave(&dsp_lock, flags);

	OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);

	OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));

	spin_unlock_irqrestore(&dsp_lock, flags);



	/* Transfer the memory block */

	while (uCount-- != 0) {

		spin_lock_irqsave(&dsp_lock, flags);

		val = InWordDsp(DSP_ReadAndClear);

		spin_unlock_irqrestore(&dsp_lock, flags);

		if(put_user(val, pusBuffer++))

			return -EFAULT;



		PaceMsaAccess(usDspBaseIO);

	}



	return 0;

}





int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,

                         unsigned uCount, unsigned long ulDSPAddr)

{

	unsigned long flags;

	unsigned short __user *pusBuffer = pvBuffer;



	/* Set the initial MSA address. No adjustments need to be made to data store addresses */

	spin_lock_irqsave(&dsp_lock, flags);

	OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);

	OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));

	spin_unlock_irqrestore(&dsp_lock, flags);



	/* Transfer the memory block */

	while (uCount-- != 0) {

		unsigned short val;

		if(get_user(val, pusBuffer++))

			return -EFAULT;

		spin_lock_irqsave(&dsp_lock, flags);

		OutWordDsp(DSP_MsaDataDSISHigh, val);

		spin_unlock_irqrestore(&dsp_lock, flags);



		PaceMsaAccess(usDspBaseIO);

	}



	return 0;

}





int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,

                        unsigned uCount, unsigned long ulDSPAddr)

{

	unsigned long flags;

	unsigned short __user *pusBuffer = pvBuffer;



	/*

	* Set the initial MSA address. To convert from an instruction store

	* address to an MSA address

	* shift the address two bits to the left and set bit 22

	*/

	ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);

	spin_lock_irqsave(&dsp_lock, flags);

	OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);

	OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));

	spin_unlock_irqrestore(&dsp_lock, flags);



	/* Transfer the memory block */

	while (uCount-- != 0) {

		unsigned short val_lo, val_hi;

		spin_lock_irqsave(&dsp_lock, flags);

		val_lo = InWordDsp(DSP_MsaDataISLow);

		val_hi = InWordDsp(DSP_MsaDataDSISHigh);

		spin_unlock_irqrestore(&dsp_lock, flags);

		if(put_user(val_lo, pusBuffer++))

			return -EFAULT;

		if(put_user(val_hi, pusBuffer++))

			return -EFAULT;



		PaceMsaAccess(usDspBaseIO);



	}



	return 0;

}





int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,

                         unsigned uCount, unsigned long ulDSPAddr)

{

	unsigned long flags;

	unsigned short __user *pusBuffer = pvBuffer;



	/*

	* Set the initial MSA address. To convert from an instruction store

	* address to an MSA address

	* shift the address two bits to the left and set bit 22

	*/

	ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);

	spin_lock_irqsave(&dsp_lock, flags);

	OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);

	OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));

	spin_unlock_irqrestore(&dsp_lock, flags);



	/* Transfer the memory block */

	while (uCount-- != 0) {

		unsigned short val_lo, val_hi;

		if(get_user(val_lo, pusBuffer++))

			return -EFAULT;

		if(get_user(val_hi, pusBuffer++))

			return -EFAULT;

		spin_lock_irqsave(&dsp_lock, flags);

		OutWordDsp(DSP_MsaDataISLow, val_lo);

		OutWordDsp(DSP_MsaDataDSISHigh, val_hi);

		spin_unlock_irqrestore(&dsp_lock, flags);



		PaceMsaAccess(usDspBaseIO);

	}



	return 0;

}





int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,

                          unsigned short *pusIPCSource)

{

	unsigned long flags;

	DSP_HBRIDGE_CONTROL rHBridgeControl;



	/*

	* Disable DSP to PC interrupts, read the interrupt register,

	* clear the pending IPC bits, and reenable DSP to PC interrupts

	*/

	spin_lock_irqsave(&dsp_lock, flags);

	MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);

	rHBridgeControl.EnableDspInt = false;

	OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));



	*pusIPCSource = InWordDsp(DSP_Interrupt);

	OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource));



	rHBridgeControl.EnableDspInt = true;

	OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));

	spin_unlock_irqrestore(&dsp_lock, flags);



	return 0;

}