Commit c11684cc authored by Jun Nie's avatar Jun Nie Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: blend pipes per mixer pairs config 



Currently, only 2 pipes are used at most for a plane. A stage structure
describes the configuration for a mixer pair. So only one stage is needed
for current usage cases. The quad-pipe case will be added in future and 2
stages are used in the case. So extend the stage to an array with array
size STAGES_PER_PLANE and blend pipes per mixer pair with configuration in
the stage structure.

Signed-off-by: default avatarJun Nie <jun.nie@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarJessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/675412/
Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-7-ff6232e3472f@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent aed75641

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

+31 −18
Original line number Diff line number Diff line
@@ -400,7 +400,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) 
static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,

				       struct drm_plane *plane,

				       struct dpu_crtc_mixer *mixer,

				       u32 num_mixers,

				       u32 lms_in_pair,

				       enum dpu_stage stage,

				       const struct msm_format *format,

				       uint64_t modifier,
@@ -434,7 +434,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, 
	stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index;



	/* blend config update */

	for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)

	for (lm_idx = 0; lm_idx < lms_in_pair; lm_idx++)

		mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx);

}
@@ -449,7 +449,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 
	struct dpu_plane_state *pstate = NULL;

	const struct msm_format *format;

	struct dpu_hw_ctl *ctl = mixer->lm_ctl;

	u32 lm_idx, i;

	u32 lm_idx, stage, i, pipe_idx, head_pipe_in_stage, lms_in_pair;

	bool bg_alpha_enable = false;

	DECLARE_BITMAP(active_fetch, SSPP_MAX);

	DECLARE_BITMAP(active_pipes, SSPP_MAX);
@@ -472,16 +472,25 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 
		if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)

			bg_alpha_enable = true;



		for (i = 0; i < PIPES_PER_PLANE; i++) {

			if (!pstate->pipe[i].sspp)

		/* loop pipe per mixer pair with config in stage structure */

		for (stage = 0; stage < STAGES_PER_PLANE; stage++) {

			head_pipe_in_stage = stage * PIPES_PER_STAGE;

			for (i = 0; i < PIPES_PER_STAGE; i++) {

				pipe_idx = i + head_pipe_in_stage;

				if (!pstate->pipe[pipe_idx].sspp)

					continue;

			set_bit(pstate->pipe[i].sspp->idx, active_fetch);

			set_bit(pstate->pipe[i].sspp->idx, active_pipes);

				lms_in_pair = min(cstate->num_mixers - (stage * PIPES_PER_STAGE),

						  PIPES_PER_STAGE);

				set_bit(pstate->pipe[pipe_idx].sspp->idx, active_fetch);

				set_bit(pstate->pipe[pipe_idx].sspp->idx, active_pipes);

				_dpu_crtc_blend_setup_pipe(crtc, plane,

						   mixer, cstate->num_mixers,

							   &mixer[head_pipe_in_stage],

							   lms_in_pair,

							   pstate->stage,

							   format, fb ? fb->modifier : 0,

						   &pstate->pipe[i], i, stage_cfg);

							   &pstate->pipe[pipe_idx], i,

							   &stage_cfg[stage]);

			}

		}



		/* blend config update */
@@ -517,7 +526,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) 
	struct dpu_crtc_mixer *mixer = cstate->mixers;

	struct dpu_hw_ctl *ctl;

	struct dpu_hw_mixer *lm;

	struct dpu_hw_stage_cfg stage_cfg;

	struct dpu_hw_stage_cfg stage_cfg[STAGES_PER_PLANE];

	DECLARE_BITMAP(active_lms, LM_MAX);

	int i;
@@ -538,10 +547,10 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) 
	}



	/* initialize stage cfg */

	memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));

	memset(&stage_cfg, 0, sizeof(stage_cfg));

	memset(active_lms, 0, sizeof(active_lms));



	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);

	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, stage_cfg);



	for (i = 0; i < cstate->num_mixers; i++) {

		ctl = mixer[i].lm_ctl;
@@ -562,13 +571,17 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) 
			mixer[i].mixer_op_mode,

			ctl->idx - CTL_0);



		/*

		 * call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg.

		 * stage data is shared between PIPES_PER_STAGE pipes.

		 */

		if (ctl->ops.setup_blendstage)

			ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,

						  &stage_cfg);

				&stage_cfg[i / PIPES_PER_STAGE]);



		if (lm->ops.setup_blendstage)

			lm->ops.setup_blendstage(lm, mixer[i].hw_lm->idx,

						 &stage_cfg);

				&stage_cfg[i / PIPES_PER_STAGE]);

	}

}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h

+2 −1
Original line number Diff line number Diff line
@@ -34,8 +34,9 @@ 
#define DPU_MAX_PLANES			4

#endif



#define PIPES_PER_PLANE			2

#define STAGES_PER_PLANE		1

#define PIPES_PER_STAGE			2

#define PIPES_PER_PLANE			(PIPES_PER_STAGE * STAGES_PER_PLANE)

#ifndef DPU_MAX_DE_CURVES

#define DPU_MAX_DE_CURVES		3

#endif