Commit c12603e7 authored by Xiao Wang's avatar Xiao Wang Committed by Daniel Borkmann
Browse files

riscv, bpf: Optimize zextw insn with Zba extension 



The Zba extension provides add.uw insn which can be used to implement
zext.w with rs2 set as ZERO.

Signed-off-by: default avatarXiao Wang <xiao.w.wang@intel.com>
Signed-off-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
Tested-by: default avatarPu Lehui <pulehui@huawei.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarPu Lehui <pulehui@huawei.com>
Link: https://lore.kernel.org/bpf/20240516090430.493122-1-xiao.w.wang@intel.com
parent ecec1887

arch/riscv/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -595,6 +595,18 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO 
	def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)

	depends on AS_HAS_OPTION_ARCH



config RISCV_ISA_ZBA

	bool "Zba extension support for bit manipulation instructions"

	default y

	help

	   Add support for enabling optimisations in the kernel when the Zba

	   extension is detected at boot.



	   The Zba extension provides instructions to accelerate the generation

	   of addresses that index into arrays of basic data types.



	   If you don't know what to do here, say Y.



config RISCV_ISA_ZBB

	bool "Zbb extension support for bit manipulation instructions"

	depends on TOOLCHAIN_HAS_ZBB

arch/riscv/net/bpf_jit.h

+18 −0
Original line number Diff line number Diff line
@@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) 
	return IS_ENABLED(CONFIG_RISCV_ISA_C);

}



static inline bool rvzba_enabled(void)

{

	return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);

}



static inline bool rvzbb_enabled(void)

{

	return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
@@ -939,6 +944,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2) 
	return rv_css_insn(0x7, imm, rs2, 0x2);

}



/* RV64-only ZBA instructions. */



static inline u32 rvzba_zextw(u8 rd, u8 rs1)

{

	/* add.uw rd, rs1, ZERO */

	return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);

}



#endif /* __riscv_xlen == 64 */



/* Helper functions that emit RVC instructions when possible. */
@@ -1161,6 +1174,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx) 


static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)

{

	if (rvzba_enabled()) {

		emit(rvzba_zextw(rd, rs), ctx);

		return;

	}



	emit_slli(rd, rs, 32, ctx);

	emit_srli(rd, rd, 32, ctx);

}