Unverified Commit c156ef57 authored by Nitin Gote's avatar Nitin Gote Committed by Rodrigo Vivi
Browse files

drm/i915/gt: fix typos in i915/gt files. 



Fix all typos in files under drm/i915/gt reported by codespell tool.

v2: Fix grammar mistake in comment. <Andi>

v3: Correct typo in commit log. <Krzysztof Niemiec>

Signed-off-by: default avatarNitin Gote <nitin.r.gote@intel.com>
Reviewed-by: default avatarKrzysztof Niemiec <krzysztof.niemiec@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250120081517.3237326-2-nitin.r.gote@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 1efd5384

drivers/gpu/drm/i915/gt/gen2_engine_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) 
	return __gen2_emit_breadcrumb(rq, cs, 8, 8);

}



/* Just userspace ABI convention to limit the wa batch bo to a resonable size */

/* Just userspace ABI convention to limit the wa batch bo to a reasonable size */

#define I830_BATCH_LIMIT SZ_256K

#define I830_TLB_ENTRIES (2)

#define I830_WA_SIZE max(I830_TLB_ENTRIES * SZ_4K, I830_BATCH_LIMIT)

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+4 −4
Original line number Diff line number Diff line
@@ -308,7 +308,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 
			/*

			 * There is a discrepancy here between the size reported

			 * by the register and the size of the context layout

			 * in the docs. Both are described as authorative!

			 * in the docs. Both are described as authoritative!

			 *

			 * The discrepancy is on the order of a few cachelines,

			 * but the total is under one page (4k), which is our
@@ -845,7 +845,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) 
 * Note that we have a catch-22 situation where we need to be able to access

 * the blitter forcewake domain to read the engine fuses, but at the same time

 * we need to know which engines are available on the system to know which

 * forcewake domains are present. We solve this by intializing the forcewake

 * forcewake domains are present. We solve this by initializing the forcewake

 * domains based on the full engine mask in the platform capabilities before

 * calling this function and pruning the domains for fused-off engines

 * afterwards.
@@ -1411,7 +1411,7 @@ create_ggtt_bind_context(struct intel_engine_cs *engine) 


	/*

	 * MI_UPDATE_GTT can insert up to 511 PTE entries and there could be multiple

	 * bind requets at a time so get a bigger ring.

	 * bind requests at a time so get a bigger ring.

	 */

	return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,

						  I915_GEM_HWS_GGTT_BIND_ADDR,
@@ -1533,7 +1533,7 @@ int intel_engines_init(struct intel_gt *gt) 


/**

 * intel_engine_cleanup_common - cleans up the engine state created by

 *                                the common initiailizers.

 *                                the common initializers.

 * @engine: Engine to cleanup.

 *

 * This cleans up everything created by the common helpers.

drivers/gpu/drm/i915/gt/intel_engine_types.h

+2 −2
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ struct intel_engine_execlists { 
	 */

	struct i915_request * const *active;

	/**

	 * @inflight: the set of contexts submitted and acknowleged by HW

	 * @inflight: the set of contexts submitted and acknowledged by HW

	 *

	 * The set of inflight contexts is managed by reading CS events

	 * from the HW. On a context-switch event (not preemption), we
@@ -260,7 +260,7 @@ struct intel_engine_execlists { 
	unsigned int port_mask;



	/**

	 * @virtual: Queue of requets on a virtual engine, sorted by priority.

	 * @virtual: Queue of requests on a virtual engine, sorted by priority.

	 * Each RB entry is a struct i915_priolist containing a list of requests

	 * of the same priority.

	 */

drivers/gpu/drm/i915/gt/intel_gt_irq.c

+1 −1
Original line number Diff line number Diff line
@@ -480,7 +480,7 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt) 
	gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(1), ~gt_interrupts[1], gt_interrupts[1]);

	/*

	 * RPS interrupts will get enabled/disabled on demand when RPS itself

	 * is enabled/disabled. Same wil be the case for GuC interrupts.

	 * is enabled/disabled. Same will be the case for GuC interrupts.

	 */

	gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(2), gt->pm_imr, gt->pm_ier);

	gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(3), ~gt_interrupts[3], gt_interrupts[3]);

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

+1 −1
Original line number Diff line number Diff line
@@ -239,7 +239,7 @@ static u32 rw_with_mcr_steering_fw(struct intel_gt *gt, 
		 * to remain in multicast mode for reads.  There's no real

		 * downside to this, so we'll just go ahead and do so on all

		 * platforms; we'll only clear the multicast bit from the mask

		 * when exlicitly doing a write operation.

		 * when explicitly doing a write operation.

		 */

		if (rw_flag == FW_REG_WRITE)

			mcr_mask |= GEN11_MCR_MULTICAST;