Commit c1668520 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'riscv-for-linus-6.13-mw1' of... 

Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux into HEAD

RISC-V Paches for the 6.13 Merge Window, Part 1

* Support for pointer masking in userspace,
* Support for probing vector misaligned access performance.
* Support for qspinlock on systems with Zacas and Zabha.
parents 1508bae3 8d4f1e05

Documentation/arch/riscv/hwprobe.rst

+19 −0
Original line number Diff line number Diff line
@@ -239,6 +239,9 @@ The following keys are defined: 
       ratified in commit 98918c844281 ("Merge pull request #1217 from

       riscv/zawrs") of riscv-isa-manual.



  * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as

       defined in version 1.0 of the RISC-V Pointer Masking extensions.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.
@@ -274,3 +277,19 @@ The following keys are defined: 
  represent the highest userspace virtual address usable.



* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.



* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the

     performance of misaligned vector accesses on the selected set of processors.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned

    vector accesses is unknown.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector

    registers are slower than the equivalent quantity of byte accesses via vector registers.

    Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector

    registers are faster than the equivalent quantity of byte accesses via vector registers.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are

    not supported at all and will generate a misaligned address fault.

Documentation/arch/riscv/uabi.rst

+16 −0
Original line number Diff line number Diff line
@@ -68,3 +68,19 @@ Misaligned accesses 
Misaligned scalar accesses are supported in userspace, but they may perform

poorly.  Misaligned vector accesses are only supported if the Zicclsm extension

is supported.



Pointer masking

---------------



Support for pointer masking in userspace (the Supm extension) is provided via

the ``PR_SET_TAGGED_ADDR_CTRL`` and ``PR_GET_TAGGED_ADDR_CTRL`` ``prctl()``

operations. Pointer masking is disabled by default. To enable it, userspace

must call ``PR_SET_TAGGED_ADDR_CTRL`` with the ``PR_PMLEN`` field set to the

number of mask/tag bits needed by the application. ``PR_PMLEN`` is interpreted

as a lower bound; if the kernel is unable to satisfy the request, the

``PR_SET_TAGGED_ADDR_CTRL`` operation will fail. The actual number of tag bits

is returned in ``PR_PMLEN`` by the ``PR_GET_TAGGED_ADDR_CTRL`` operation.



Additionally, when pointer masking is enabled (``PR_PMLEN`` is greater than 0),

a tagged address ABI is supported, with the same interface and behavior as

documented for AArch64 (Documentation/arch/arm64/tagged-address-abi.rst).

Documentation/devicetree/bindings/riscv/extensions.yaml

+30 −0
Original line number Diff line number Diff line
@@ -128,6 +128,18 @@ properties: 
            changes to interrupts as frozen at commit ccbddab ("Merge pull

            request #42 from riscv/jhauser-2023-RC4") of riscv-aia.



        - const: smmpm

          description: |

            The standard Smmpm extension for M-mode pointer masking as

            ratified at commit d70011dde6c2 ("Update to ratified state")

            of riscv-j-extension.



        - const: smnpm

          description: |

            The standard Smnpm extension for next-mode pointer masking as

            ratified at commit d70011dde6c2 ("Update to ratified state")

            of riscv-j-extension.



        - const: smstateen

          description: |

            The standard Smstateen extension for controlling access to CSRs
@@ -147,6 +159,12 @@ properties: 
            and mode-based filtering as ratified at commit 01d1df0 ("Add ability

            to manually trigger workflow. (#2)") of riscv-count-overflow.



        - const: ssnpm

          description: |

            The standard Ssnpm extension for next-mode pointer masking as

            ratified at commit d70011dde6c2 ("Update to ratified state")

            of riscv-j-extension.



        - const: sstc

          description: |

            The standard Sstc supervisor-level extension for time compare as
@@ -178,6 +196,12 @@ properties: 
            as ratified at commit 4a69197e5617 ("Update to ratified state") of

            riscv-svvptc.



        - const: zabha

          description: |

            The Zabha extension for Byte and Halfword Atomic Memory Operations

            as ratified at commit 49f49c842ff9 ("Update to Rafified state") of

            riscv-zabha.



        - const: zacas

          description: |

            The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
@@ -290,6 +314,12 @@ properties: 
            in commit 64074bc ("Update version numbers for Zfh/Zfinx") of

            riscv-isa-manual.



        - const: ziccrse

          description:

            The standard Ziccrse extension which provides forward progress

            guarantee on LR/SC sequences, as ratified in commit b1d806605f87

            ("Updated to ratified state.") of the riscv profiles specification.



        - const: zk

          description:

            The standard Zk Standard Scalar cryptography extension as ratified

Documentation/features/locking/queued-spinlocks/arch-support.txt

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 
    |    openrisc: |  ok  |

    |      parisc: | TODO |

    |     powerpc: |  ok  |

    |       riscv: | TODO |

    |       riscv: |  ok  |

    |        s390: | TODO |

    |          sh: | TODO |

    |       sparc: |  ok  |

arch/riscv/Kconfig

+136 −2
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ config RISCV 
	select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP

	select ARCH_WANTS_NO_INSTR

	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE

	select ARCH_WEAK_RELEASE_ACQUIRE if ARCH_USE_QUEUED_SPINLOCKS

	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU

	select BUILDTIME_TABLE_SORT if MMU

	select CLINT_TIMER if RISCV_M_MODE
@@ -115,6 +116,7 @@ config RISCV 
	select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO

	select HARDIRQS_SW_RESEND

	select HAS_IOPORT if MMU

	select HAVE_ALIGNED_STRUCT_PAGE

	select HAVE_ARCH_AUDITSYSCALL

	select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP

	select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT
@@ -506,6 +508,39 @@ config NODES_SHIFT 
	  Specify the maximum number of NUMA Nodes available on the target

	  system.  Increases memory reserved to accommodate various tables.



choice

	prompt "RISC-V spinlock type"

	default RISCV_COMBO_SPINLOCKS



config RISCV_TICKET_SPINLOCKS

	bool "Using ticket spinlock"



config RISCV_QUEUED_SPINLOCKS

	bool "Using queued spinlock"

	depends on SMP && MMU && NONPORTABLE

	select ARCH_USE_QUEUED_SPINLOCKS

	help

	  The queued spinlock implementation requires the forward progress

	  guarantee of cmpxchg()/xchg() atomic operations: CAS with Zabha or

	  LR/SC with Ziccrse provide such guarantee.



	  Select this if and only if Zabha or Ziccrse is available on your

	  platform, RISCV_QUEUED_SPINLOCKS must not be selected for platforms

	  without one of those extensions.



	  If unsure, select RISCV_COMBO_SPINLOCKS, which will use qspinlocks

	  when supported and otherwise ticket spinlocks.



config RISCV_COMBO_SPINLOCKS

	bool "Using combo spinlock"

	depends on SMP && MMU

	select ARCH_USE_QUEUED_SPINLOCKS

	help

	  Embed both queued spinlock and ticket lock so that the spinlock

	  implementation can be chosen at runtime.



endchoice



config RISCV_ALTERNATIVE

	bool

	depends on !XIP_KERNEL
@@ -531,6 +566,17 @@ config RISCV_ISA_C 


	  If you don't know what to do here, say Y.



config RISCV_ISA_SUPM

	bool "Supm extension for userspace pointer masking"

	depends on 64BIT

	default y

	help

	  Add support for pointer masking in userspace (Supm) when the

	  underlying hardware extension (Smnpm or Ssnpm) is detected at boot.



	  If this option is disabled, userspace will be unable to use

	  the prctl(PR_{SET,GET}_TAGGED_ADDR_CTRL) API.



config RISCV_ISA_SVNAPOT

	bool "Svnapot extension support for supervisor mode NAPOT pages"

	depends on 64BIT && MMU
@@ -632,6 +678,40 @@ config RISCV_ISA_ZAWRS 
	  use of these instructions in the kernel when the Zawrs extension is

	  detected at boot.



config TOOLCHAIN_HAS_ZABHA

	bool

	default y

	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha)

	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha)

	depends on AS_HAS_OPTION_ARCH



config RISCV_ISA_ZABHA

	bool "Zabha extension support for atomic byte/halfword operations"

	depends on TOOLCHAIN_HAS_ZABHA

	depends on RISCV_ALTERNATIVE

	default y

	help

	  Enable the use of the Zabha ISA-extension to implement kernel

	  byte/halfword atomic memory operations when it is detected at boot.



	  If you don't know what to do here, say Y.



config TOOLCHAIN_HAS_ZACAS

	bool

	default y

	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas)

	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas)

	depends on AS_HAS_OPTION_ARCH



config RISCV_ISA_ZACAS

	bool "Zacas extension support for atomic CAS"

	depends on TOOLCHAIN_HAS_ZACAS

	depends on RISCV_ALTERNATIVE

	default y

	help

	  Enable the use of the Zacas ISA-extension to implement kernel atomic

	  cmpxchg operations when it is detected at boot.



	  If you don't know what to do here, say Y.



config TOOLCHAIN_HAS_ZBB
@@ -785,10 +865,24 @@ config THREAD_SIZE_ORDER 


config RISCV_MISALIGNED

	bool

	help

	  Embed support for detecting and emulating misaligned

	  scalar or vector loads and stores.



config RISCV_SCALAR_MISALIGNED

	bool

	select RISCV_MISALIGNED

	select SYSCTL_ARCH_UNALIGN_ALLOW

	help

	  Embed support for emulating misaligned loads and stores.



config RISCV_VECTOR_MISALIGNED

	bool

	select RISCV_MISALIGNED

	depends on RISCV_ISA_V

	help

	  Enable detecting support for vector misaligned loads and stores.



choice

	prompt "Unaligned Accesses Support"

	default RISCV_PROBE_UNALIGNED_ACCESS
@@ -800,7 +894,7 @@ choice 


config RISCV_PROBE_UNALIGNED_ACCESS

	bool "Probe for hardware unaligned access support"

	select RISCV_MISALIGNED

	select RISCV_SCALAR_MISALIGNED

	help

	  During boot, the kernel will run a series of tests to determine the

	  speed of unaligned accesses. This probing will dynamically determine
@@ -811,7 +905,7 @@ config RISCV_PROBE_UNALIGNED_ACCESS 


config RISCV_EMULATED_UNALIGNED_ACCESS

	bool "Emulate unaligned access where system support is missing"

	select RISCV_MISALIGNED

	select RISCV_SCALAR_MISALIGNED

	help

	  If unaligned memory accesses trap into the kernel as they are not

	  supported by the system, the kernel will emulate the unaligned
@@ -840,6 +934,46 @@ config RISCV_EFFICIENT_UNALIGNED_ACCESS 


endchoice



choice

	prompt "Vector unaligned Accesses Support"

	depends on RISCV_ISA_V

	default RISCV_PROBE_VECTOR_UNALIGNED_ACCESS

	help

	  This determines the level of support for vector unaligned accesses. This

	  information is used by the kernel to perform optimizations. It is also

	  exposed to user space via the hwprobe syscall. The hardware will be

	  probed at boot by default.



config RISCV_PROBE_VECTOR_UNALIGNED_ACCESS

	bool "Probe speed of vector unaligned accesses"

	select RISCV_VECTOR_MISALIGNED

	depends on RISCV_ISA_V

	help

	  During boot, the kernel will run a series of tests to determine the

	  speed of vector unaligned accesses if they are supported. This probing

	  will dynamically determine the speed of vector unaligned accesses on

	  the underlying system if they are supported.



config RISCV_SLOW_VECTOR_UNALIGNED_ACCESS

	bool "Assume the system supports slow vector unaligned memory accesses"

	depends on NONPORTABLE

	help

	  Assume that the system supports slow vector unaligned memory accesses. The

	  kernel and userspace programs may not be able to run at all on systems

	  that do not support unaligned memory accesses.



config RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS

	bool "Assume the system supports fast vector unaligned memory accesses"

	depends on NONPORTABLE

	help

	  Assume that the system supports fast vector unaligned memory accesses. When

	  enabled, this option improves the performance of the kernel on such

	  systems. However, the kernel and userspace programs will run much more

	  slowly, or will not be able to run at all, on systems that do not

	  support efficient unaligned memory accesses.



endchoice



source "arch/riscv/Kconfig.vendor"



endmenu # "Platform type"