Commit c1bb69a2 authored by Himal Prasad Ghimiray's avatar Himal Prasad Ghimiray
Browse files

drm/xe/svm: Consult madvise preferred location in prefetch 



When prefetch region is DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, prefetch svm
ranges to preferred location provided by madvise.

v2 (Matthew Brost)
- Fix region, devmem_fd usages
- consult madvise is applicable for other vma's too.

v3
- Fix atomic handling

v4
- Fix xe_svm_range_validate to check for
  DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC too.

Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Link: https://lore.kernel.org/r/20250821173104.3030148-14-himal.prasad.ghimiray@intel.com


Signed-off-by: default avatarHimal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
parent fa1a82c9

drivers/gpu/drm/xe/xe_vm.c

+30 −17
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
#include "xe_res_cursor.h"

#include "xe_svm.h"

#include "xe_sync.h"

#include "xe_tile.h"

#include "xe_trace_bo.h"

#include "xe_wa.h"

#include "xe_hmm.h"
@@ -2400,9 +2401,10 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_vma_ops *vops, 
				__xe_vm_needs_clear_scratch_pages(vm, flags);

		} else if (__op->op == DRM_GPUVA_OP_PREFETCH) {

			struct xe_vma *vma = gpuva_to_vma(op->base.prefetch.va);

			struct xe_tile *tile;

			struct xe_svm_range *svm_range;

			struct drm_gpusvm_ctx ctx = {};

			struct xe_tile *tile;

			struct drm_pagemap *dpagemap;

			u8 id, tile_mask = 0;

			u32 i;
@@ -2419,8 +2421,24 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_vma_ops *vops, 
				tile_mask |= 0x1 << id;



			xa_init_flags(&op->prefetch_range.range, XA_FLAGS_ALLOC);

			op->prefetch_range.region = prefetch_region;

			op->prefetch_range.ranges_count = 0;

			tile = NULL;



			if (prefetch_region == DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC) {

				dpagemap = xe_vma_resolve_pagemap(vma,

								  xe_device_get_root_tile(vm->xe));

				/*

				 * TODO: Once multigpu support is enabled will need

				 * something to dereference tile from dpagemap.

				 */

				if (dpagemap)

					tile = xe_device_get_root_tile(vm->xe);

			} else if (prefetch_region) {

				tile = &vm->xe->tiles[region_to_mem_type[prefetch_region] -

						      XE_PL_VRAM0];

			}



			op->prefetch_range.tile = tile;

alloc_next_range:

			svm_range = xe_svm_range_find_or_insert(vm, addr, vma, &ctx);
@@ -2439,7 +2457,7 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_vma_ops *vops, 
				goto unwind_prefetch_ops;

			}



			if (xe_svm_range_validate(vm, svm_range, tile_mask, !!prefetch_region)) {

			if (xe_svm_range_validate(vm, svm_range, tile_mask, !!tile)) {

				xe_svm_range_debug(svm_range, "PREFETCH - RANGE IS VALID");

				goto check_next_range;

			}
@@ -2935,30 +2953,26 @@ static int prefetch_ranges(struct xe_vm *vm, struct xe_vma_op *op) 
{

	bool devmem_possible = IS_DGFX(vm->xe) && IS_ENABLED(CONFIG_DRM_XE_PAGEMAP);

	struct xe_vma *vma = gpuva_to_vma(op->base.prefetch.va);

	struct xe_tile *tile = op->prefetch_range.tile;

	int err = 0;



	struct xe_svm_range *svm_range;

	struct drm_gpusvm_ctx ctx = {};

	struct xe_tile *tile;

	unsigned long i;

	u32 region;



	if (!xe_vma_is_cpu_addr_mirror(vma))

		return 0;



	region = op->prefetch_range.region;



	ctx.read_only = xe_vma_read_only(vma);

	ctx.devmem_possible = devmem_possible;

	ctx.check_pages_threshold = devmem_possible ? SZ_64K : 0;



	/* TODO: Threading the migration */

	xa_for_each(&op->prefetch_range.range, i, svm_range) {

		if (!region)

		if (!tile)

			xe_svm_range_migrate_to_smem(vm, svm_range);



		if (xe_svm_range_needs_migrate_to_vram(svm_range, vma, region)) {

			tile = &vm->xe->tiles[region_to_mem_type[region] - XE_PL_VRAM0];

		if (xe_svm_range_needs_migrate_to_vram(svm_range, vma, !!tile)) {

			err = xe_svm_alloc_vram(tile, svm_range, &ctx);

			if (err) {

				drm_dbg(&vm->xe->drm, "VRAM allocation failed, retry from userspace, asid=%u, gpusvm=%p, errno=%pe\n",
@@ -3021,12 +3035,11 @@ static int op_lock_and_prep(struct drm_exec *exec, struct xe_vm *vm, 
		struct xe_vma *vma = gpuva_to_vma(op->base.prefetch.va);

		u32 region;



		if (xe_vma_is_cpu_addr_mirror(vma))

			region = op->prefetch_range.region;

		else

		if (!xe_vma_is_cpu_addr_mirror(vma)) {

			region = op->prefetch.region;



		xe_assert(vm->xe, region <= ARRAY_SIZE(region_to_mem_type));

			xe_assert(vm->xe, region == DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC ||

				  region <= ARRAY_SIZE(region_to_mem_type));

		}



		err = vma_lock_and_validate(exec,

					    gpuva_to_vma(op->base.prefetch.va),
@@ -3444,8 +3457,8 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, 
				 op == DRM_XE_VM_BIND_OP_PREFETCH) ||

		    XE_IOCTL_DBG(xe, prefetch_region &&

				 op != DRM_XE_VM_BIND_OP_PREFETCH) ||

		    XE_IOCTL_DBG(xe, !(BIT(prefetch_region) &

				       xe->info.mem_region_mask)) ||

		    XE_IOCTL_DBG(xe,  (prefetch_region != DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC &&

				       !(BIT(prefetch_region) & xe->info.mem_region_mask))) ||

		    XE_IOCTL_DBG(xe, obj &&

				 op == DRM_XE_VM_BIND_OP_UNMAP)) {

			err = -EINVAL;

drivers/gpu/drm/xe/xe_vm_types.h

+5 −2
Original line number Diff line number Diff line
@@ -428,8 +428,11 @@ struct xe_vma_op_prefetch_range { 
	struct xarray range;

	/** @ranges_count: number of svm ranges to map */

	u32 ranges_count;

	/** @region: memory region to prefetch to */

	u32 region;

	/**

	 * @tile: Pointer to the tile structure containing memory to prefetch.

	 *        NULL if prefetch requested region is smem

	 */

	struct xe_tile *tile;

};



/** enum xe_vma_op_flags - flags for VMA operation */