Unverified Commit c1e42ec0 authored by parkeryang's avatar parkeryang Committed by Mark Brown
Browse files

ASoC: mediatek: mt8188: Add support for DMIC 



Add support for the DMIC DAIs present on the MT8188 SoC. To achieve
that, add a DAI driver for DMIC and register it during probe, and
describe the AFE routes that connect the DMIC (I004-I011) to the UL9
frontend (O002-O009).

Signed-off-by: default avatarparkeryang <Parker.Yang@mediatek.com>
Co-developed-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20250225-genio700-dmic-v2-4-3076f5b50ef7@collabora.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7d87bde2

sound/soc/mediatek/mt8188/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ snd-soc-mt8188-afe-y := \ 
	mt8188-afe-pcm.o \

	mt8188-audsys-clk.o \

	mt8188-dai-adda.o \

	mt8188-dai-dmic.o \

	mt8188-dai-etdm.o \

	mt8188-dai-pcm.o

sound/soc/mediatek/mt8188/mt8188-afe-common.h

+1 −0
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ struct mt8188_afe_private { 
int mt8188_afe_fs_timing(unsigned int rate);

/* dai register */

int mt8188_dai_adda_register(struct mtk_base_afe *afe);

int mt8188_dai_dmic_register(struct mtk_base_afe *afe);

int mt8188_dai_etdm_register(struct mtk_base_afe *afe);

int mt8188_dai_pcm_register(struct mtk_base_afe *afe);

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

+24 −0
Original line number Diff line number Diff line
@@ -652,6 +652,7 @@ static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = { 


static const struct snd_kcontrol_new o002_mix[] = {

	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I004 Switch", AFE_CONN2, 4, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0),
@@ -662,6 +663,8 @@ static const struct snd_kcontrol_new o002_mix[] = { 


static const struct snd_kcontrol_new o003_mix[] = {

	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I005 Switch", AFE_CONN3, 5, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I006 Switch", AFE_CONN3, 6, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0),
@@ -672,6 +675,8 @@ static const struct snd_kcontrol_new o003_mix[] = { 


static const struct snd_kcontrol_new o004_mix[] = {

	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I006 Switch", AFE_CONN4, 6, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I008 Switch", AFE_CONN4, 8, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0),
@@ -679,6 +684,8 @@ static const struct snd_kcontrol_new o004_mix[] = { 


static const struct snd_kcontrol_new o005_mix[] = {

	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I007 Switch", AFE_CONN5, 7, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I010 Switch", AFE_CONN5, 10, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0),
@@ -686,6 +693,7 @@ static const struct snd_kcontrol_new o005_mix[] = { 


static const struct snd_kcontrol_new o006_mix[] = {

	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I008 Switch", AFE_CONN6, 8, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0),
@@ -693,18 +701,21 @@ static const struct snd_kcontrol_new o006_mix[] = { 


static const struct snd_kcontrol_new o007_mix[] = {

	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I009 Switch", AFE_CONN7, 9, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0),

};



static const struct snd_kcontrol_new o008_mix[] = {

	SOC_DAPM_SINGLE_AUTODISABLE("I010 Switch", AFE_CONN8, 10, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0),

};



static const struct snd_kcontrol_new o009_mix[] = {

	SOC_DAPM_SINGLE_AUTODISABLE("I011 Switch", AFE_CONN9, 11, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0),

	SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0),
@@ -1275,6 +1286,18 @@ static const struct snd_soc_dapm_route mt8188_memif_routes[] = { 
	{"O002", "I070 Switch", "I070"},

	{"O003", "I071 Switch", "I071"},



	{"O002", "I004 Switch", "I004"},

	{"O003", "I005 Switch", "I005"},

	{"O003", "I006 Switch", "I006"},

	{"O004", "I006 Switch", "I006"},

	{"O004", "I008 Switch", "I008"},

	{"O005", "I007 Switch", "I007"},

	{"O005", "I010 Switch", "I010"},

	{"O006", "I008 Switch", "I008"},

	{"O007", "I009 Switch", "I009"},

	{"O008", "I010 Switch", "I010"},

	{"O009", "I011 Switch", "I011"},



	{"O034", "I000 Switch", "I000"},

	{"O035", "I001 Switch", "I001"},

	{"O034", "I002 Switch", "I002"},
@@ -3072,6 +3095,7 @@ static int mt8188_dai_memif_register(struct mtk_base_afe *afe) 
typedef int (*dai_register_cb)(struct mtk_base_afe *);

static const dai_register_cb dai_register_cbs[] = {

	mt8188_dai_adda_register,

	mt8188_dai_dmic_register,

	mt8188_dai_etdm_register,

	mt8188_dai_pcm_register,

	mt8188_dai_memif_register,

sound/soc/mediatek/mt8188/mt8188-dai-dmic.c

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sound/soc/mediatek/mt8188/mt8188-reg.h

+15 −2
Original line number Diff line number Diff line
@@ -2837,9 +2837,20 @@ 
#define PWR2_TOP_CON_DMIC3_SRC_SEL_MASK     GENMASK(16, 14)

#define PWR2_TOP_CON_DMIC2_SRC_SEL_MASK     GENMASK(13, 11)

#define PWR2_TOP_CON_DMIC1_SRC_SEL_MASK     GENMASK(10, 8)

#define PWR2_TOP_CON_DMIC8_SRC_SEL_VAL(x)   ((x) << 29)

#define PWR2_TOP_CON_DMIC7_SRC_SEL_VAL(x)   ((x) << 26)

#define PWR2_TOP_CON_DMIC6_SRC_SEL_VAL(x)   ((x) << 23)

#define PWR2_TOP_CON_DMIC5_SRC_SEL_VAL(x)   ((x) << 20)

#define PWR2_TOP_CON_DMIC4_SRC_SEL_VAL(x)   ((x) << 17)

#define PWR2_TOP_CON_DMIC3_SRC_SEL_VAL(x)   ((x) << 14)

#define PWR2_TOP_CON_DMIC2_SRC_SEL_VAL(x)   ((x) << 11)

#define PWR2_TOP_CON_DMIC1_SRC_SEL_VAL(x)   ((x) << 8)



/* PWR2_TOP_CON1 */

#define PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(x)	BIT(5 + 6 * (x))

#define PWR2_TOP_CON1_DMIC_CKDIV_ON             BIT(1)

#define PWR2_TOP_CON1_DMIC_CKDIV_ON_SHIFT       1





/* PCM_INTF_CON1 */

#define PCM_INTF_CON1_SYNC_OUT_INV     BIT(23)
@@ -2921,13 +2932,14 @@ 
#define AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL	BIT(23)

#define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL	BIT(22)

#define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL	BIT(21)



#define AFE_DMIC_UL_VOICE_MODE(x)			(((x) & GENMASK(2, 0)) << 17)

#define AFE_DMIC_UL_VOICE_MODE_MASK			GENMASK(19, 17)

#define AFE_DMIC_UL_CON0_VOCIE_MODE_8K			AFE_DMIC_UL_VOICE_MODE(0)

#define AFE_DMIC_UL_CON0_VOCIE_MODE_16K			AFE_DMIC_UL_VOICE_MODE(1)

#define AFE_DMIC_UL_CON0_VOCIE_MODE_32K			AFE_DMIC_UL_VOICE_MODE(2)

#define AFE_DMIC_UL_CON0_VOCIE_MODE_48K			AFE_DMIC_UL_VOICE_MODE(3)

#define AFE_DMIC_UL_CON0_VOCIE_MODE_96K			AFE_DMIC_UL_VOICE_MODE(4)

#define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL(x)		(((x) & GENMASK(2, 0)) << 7)

#define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL_MASK	GENMASK(9, 7)

#define AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL		BIT(10)

#define AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL		BIT(1)
@@ -2944,6 +2956,7 @@ 


/* DMIC_GAINx_CON0 */

#define DMIC_GAIN_CON0_GAIN_ON			BIT(0)

#define DMIC_GAIN_CON0_SAMPLE_PER_STEP_SHIFT	8

#define DMIC_GAIN_CON0_SAMPLE_PER_STEP_MASK	GENMASK(15, 8)



/* DMIC_GAINx_CON1 */