Commit c20eaf44 authored by Dave Jiang's avatar Dave Jiang Committed by Dan Williams
Browse files

cxl/region: Add sysfs attribute for locality attributes of CXL regions 



Add read/write latencies and bandwidth sysfs attributes for the enabled CXL
region. The bandwidth is the aggregated bandwidth of all devices that
contribute to the CXL region. The latency is the worst latency of the
device amongst all the devices that contribute to the CXL region.

Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20240308220055.2172956-11-dave.jiang@intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 3d9f4a19

Documentation/ABI/testing/sysfs-bus-cxl

+34 −0
Original line number Diff line number Diff line
@@ -552,3 +552,37 @@ Description: 
		attribute is only visible for devices supporting the

		capability. The retrieved errors are logged as kernel

		events when cxl_poison event tracing is enabled.





What:		/sys/bus/cxl/devices/regionZ/accessY/read_bandwidth

		/sys/bus/cxl/devices/regionZ/accessY/write_banwidth

Date:		Jan, 2024

KernelVersion:	v6.9

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) The aggregated read or write bandwidth of the region. The

		number is the accumulated read or write bandwidth of all CXL memory

		devices that contributes to the region in MB/s. It is

		identical data that should appear in

		/sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth or

		/sys/devices/system/node/nodeX/accessY/initiators/write_bandwidth.

		See Documentation/ABI/stable/sysfs-devices-node. access0 provides

		the number to the closest initiator and access1 provides the

		number to the closest CPU.





What:		/sys/bus/cxl/devices/regionZ/accessY/read_latency

		/sys/bus/cxl/devices/regionZ/accessY/write_latency

Date:		Jan, 2024

KernelVersion:	v6.9

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) The read or write latency of the region. The number is

		the worst read or write latency of all CXL memory devices that

		contributes to the region in nanoseconds. It is identical data

		that should appear in

		/sys/devices/system/node/nodeX/accessY/initiators/read_latency or

		/sys/devices/system/node/nodeX/accessY/initiators/write_latency.

		See Documentation/ABI/stable/sysfs-devices-node. access0 provides

		the number to the closest initiator and access1 provides the

		number to the closest CPU.

drivers/cxl/core/region.c

+94 −0
Original line number Diff line number Diff line
@@ -30,6 +30,98 @@ 


static struct cxl_region *to_cxl_region(struct device *dev);



#define __ACCESS_ATTR_RO(_level, _name) {				\

	.attr	= { .name = __stringify(_name), .mode = 0444 },		\

	.show	= _name##_access##_level##_show,			\

}



#define ACCESS_DEVICE_ATTR_RO(level, name)	\

	struct device_attribute dev_attr_access##level##_##name = __ACCESS_ATTR_RO(level, name)



#define ACCESS_ATTR_RO(level, attrib)					      \

static ssize_t attrib##_access##level##_show(struct device *dev,	      \

					  struct device_attribute *attr,      \

					  char *buf)			      \

{									      \

	struct cxl_region *cxlr = to_cxl_region(dev);			      \

									      \

	if (cxlr->coord[level].attrib == 0)				      \

		return -ENOENT;						      \

									      \

	return sysfs_emit(buf, "%u\n", cxlr->coord[level].attrib);	      \

}									      \

static ACCESS_DEVICE_ATTR_RO(level, attrib)



ACCESS_ATTR_RO(0, read_bandwidth);

ACCESS_ATTR_RO(0, read_latency);

ACCESS_ATTR_RO(0, write_bandwidth);

ACCESS_ATTR_RO(0, write_latency);



#define ACCESS_ATTR_DECLARE(level, attrib)	\

	(&dev_attr_access##level##_##attrib.attr)



static struct attribute *access0_coordinate_attrs[] = {

	ACCESS_ATTR_DECLARE(0, read_bandwidth),

	ACCESS_ATTR_DECLARE(0, write_bandwidth),

	ACCESS_ATTR_DECLARE(0, read_latency),

	ACCESS_ATTR_DECLARE(0, write_latency),

	NULL

};



ACCESS_ATTR_RO(1, read_bandwidth);

ACCESS_ATTR_RO(1, read_latency);

ACCESS_ATTR_RO(1, write_bandwidth);

ACCESS_ATTR_RO(1, write_latency);



static struct attribute *access1_coordinate_attrs[] = {

	ACCESS_ATTR_DECLARE(1, read_bandwidth),

	ACCESS_ATTR_DECLARE(1, write_bandwidth),

	ACCESS_ATTR_DECLARE(1, read_latency),

	ACCESS_ATTR_DECLARE(1, write_latency),

	NULL

};



#define ACCESS_VISIBLE(level)						\

static umode_t cxl_region_access##level##_coordinate_visible(		\

		struct kobject *kobj, struct attribute *a, int n)	\

{									\

	struct device *dev = kobj_to_dev(kobj);				\

	struct cxl_region *cxlr = to_cxl_region(dev);			\

									\

	if (a == &dev_attr_access##level##_read_latency.attr &&		\

	    cxlr->coord[level].read_latency == 0)			\

		return 0;						\

									\

	if (a == &dev_attr_access##level##_write_latency.attr &&	\

	    cxlr->coord[level].write_latency == 0)			\

		return 0;						\

									\

	if (a == &dev_attr_access##level##_read_bandwidth.attr &&	\

	    cxlr->coord[level].read_bandwidth == 0)			\

		return 0;						\

									\

	if (a == &dev_attr_access##level##_write_bandwidth.attr &&	\

	    cxlr->coord[level].write_bandwidth == 0)			\

		return 0;						\

									\

	return a->mode;							\

}



ACCESS_VISIBLE(0);

ACCESS_VISIBLE(1);



static const struct attribute_group cxl_region_access0_coordinate_group = {

	.name = "access0",

	.attrs = access0_coordinate_attrs,

	.is_visible = cxl_region_access0_coordinate_visible,

};



static const struct attribute_group cxl_region_access1_coordinate_group = {

	.name = "access1",

	.attrs = access1_coordinate_attrs,

	.is_visible = cxl_region_access1_coordinate_visible,

};



static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,

			 char *buf)

{
@@ -2069,6 +2161,8 @@ static const struct attribute_group *region_groups[] = { 
	&cxl_base_attribute_group,

	&cxl_region_group,

	&cxl_region_target_group,

	&cxl_region_access0_coordinate_group,

	&cxl_region_access1_coordinate_group,

	NULL,

};