Commit c21a764a authored by Krunoslav Kovac's avatar Krunoslav Kovac Committed by Alex Deucher
Browse files

drm/amd/display: Send PQ bit in AMD VSIF 



[WHY & HOW]
PB9 bit 5 was added to signal PQ EOTF in AMD vendor specific infoframe.
This change sets it when appropriate.

Reviewed-by: default avatarAric Cyr <aric.cyr@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarKrunoslav Kovac <krunoslav.kovac@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cc6201b7

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

+4 −2
Original line number Diff line number Diff line
@@ -693,10 +693,12 @@ static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf, 
	if (app_tf != TRANSFER_FUNC_UNKNOWN) {

		infopacket->valid = true;



		if (app_tf != TRANSFER_FUNC_PQ2084) {

		if (app_tf == TRANSFER_FUNC_PQ2084)

			infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]

		else {

			infopacket->sb[6] |= 0x08;  // PB6 = [Bit 3 = Native Color Active]

			if (app_tf == TRANSFER_FUNC_GAMMA_22)

				infopacket->sb[9] |= 0x04;  // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]

				infopacket->sb[9] |= 0x04;  // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]

		}

	}

}