Commit c223376b authored by Li Ma's avatar Li Ma Committed by Alex Deucher
Browse files

drm/amd/swsmu: add MALL init support workaround for smu_v14_0_1 



[Why]
SMU firmware has not supported MALL PG.

[How]
Disable MALL PG and make it always on until SMU firmware is ready.

Signed-off-by: default avatarLi Ma <li.ma@amd.com>
Reviewed-by: default avatarTim Huang <Tim.Huang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f2661062

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+13 −0
Original line number Diff line number Diff line
@@ -324,6 +324,18 @@ static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 
	return ret;

}



static int smu_set_mall_enable(struct smu_context *smu)

{

	int ret = 0;



	if (!smu->ppt_funcs->set_mall_enable)

		return 0;



	ret = smu->ppt_funcs->set_mall_enable(smu);



	return ret;

}



/**

 * smu_dpm_set_power_gate - power gate/ungate the specific IP block

 *
@@ -1791,6 +1803,7 @@ static int smu_hw_init(void *handle) 
		smu_dpm_set_jpeg_enable(smu, true);

		smu_dpm_set_vpe_enable(smu, true);

		smu_dpm_set_umsch_mm_enable(smu, true);

		smu_set_mall_enable(smu);

		smu_set_gfx_cgpg(smu, true);

	}

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+5 −0
Original line number Diff line number Diff line
@@ -1394,6 +1394,11 @@ struct pptable_funcs { 
	 */

	int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);



	/**

	 * @set_mall_enable: Init MALL power gating control.

	 */

	int (*set_mall_enable)(struct smu_context *smu);



	/**

	 * @notify_rlc_state: Notify RLC power state to SMU.

	 */

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h

+2 −2
Original line number Diff line number Diff line
@@ -106,8 +106,8 @@ 
#define PPSMC_MSG_DisableLSdma                  0x35 ///< Disable LSDMA

#define PPSMC_MSG_SetSoftMaxVpe                 0x36 ///<

#define PPSMC_MSG_SetSoftMinVpe                 0x37 ///<

#define PPSMC_MSG_AllocMALLCache                0x38 ///< Allocating MALL Cache

#define PPSMC_MSG_ReleaseMALLCache              0x39 ///< Releasing MALL Cache

#define PPSMC_MSG_MALLPowerController           0x38 ///< Set MALL control

#define PPSMC_MSG_MALLPowerState                0x39 ///< Enter/Exit MALL PG

#define PPSMC_Message_Count                     0x3A ///< Total number of PPSMC messages

/** @}*/

drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h

+3 −1
Original line number Diff line number Diff line
@@ -272,7 +272,9 @@ 
	__SMU_DUMMY_MAP(SetSoftMinVpe), \

	__SMU_DUMMY_MAP(GetMetricsVersion), \

	__SMU_DUMMY_MAP(EnableUCLKShadow), \

	__SMU_DUMMY_MAP(RmaDueToBadPageThreshold),

	__SMU_DUMMY_MAP(RmaDueToBadPageThreshold), \

	__SMU_DUMMY_MAP(MALLPowerController), \

	__SMU_DUMMY_MAP(MALLPowerState),



#undef __SMU_DUMMY_MAP

#define __SMU_DUMMY_MAP(type)	SMU_MSG_##type

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

+73 −0
Original line number Diff line number Diff line
@@ -52,6 +52,19 @@ 
#define mmMP1_SMN_C2PMSG_90			0x029a

#define mmMP1_SMN_C2PMSG_90_BASE_IDX		    0



/* MALLPowerController message arguments (Defines for the Cache mode control) */

#define SMU_MALL_PMFW_CONTROL 0

#define SMU_MALL_DRIVER_CONTROL 1



/*

 * MALLPowerState message arguments

 * (Defines for the Allocate/Release Cache mode if in driver mode)

 */

#define SMU_MALL_EXIT_PG 0

#define SMU_MALL_ENTER_PG 1



#define SMU_MALL_PG_CONFIG_DEFAULT SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON



#define FEATURE_MASK(feature) (1ULL << feature)

#define SMC_DPM_FEATURE ( \

	FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -66,6 +79,12 @@ 
	FEATURE_MASK(FEATURE_GFX_DPM_BIT)	| \

	FEATURE_MASK(FEATURE_VPE_DPM_BIT))



enum smu_mall_pg_config {

	SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0,

	SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON = 1,

	SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_OFF = 2,

};



static struct cmn2asic_msg_mapping smu_v14_0_0_message_map[SMU_MSG_MAX_COUNT] = {

	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,				1),

	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetPmfwVersion,			1),
@@ -113,6 +132,8 @@ static struct cmn2asic_msg_mapping smu_v14_0_0_message_map[SMU_MSG_MAX_COUNT] = 
	MSG_MAP(PowerDownUmsch,                 PPSMC_MSG_PowerDownUmsch,			1),

	MSG_MAP(SetSoftMaxVpe,                  PPSMC_MSG_SetSoftMaxVpe,			1),

	MSG_MAP(SetSoftMinVpe,                  PPSMC_MSG_SetSoftMinVpe,			1),

	MSG_MAP(MALLPowerController,            PPSMC_MSG_MALLPowerController,		1),

	MSG_MAP(MALLPowerState,                 PPSMC_MSG_MALLPowerState,			1),

};



static struct cmn2asic_mapping smu_v14_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
@@ -1423,6 +1444,57 @@ static int smu_v14_0_common_get_dpm_table(struct smu_context *smu, struct dpm_cl 
	return 0;

}



static int smu_v14_0_1_init_mall_power_gating(struct smu_context *smu, enum smu_mall_pg_config pg_config)

{

	struct amdgpu_device *adev = smu->adev;

	int ret = 0;



	if (pg_config == SMU_MALL_PG_CONFIG_PMFW_CONTROL) {

		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_MALLPowerController,

								SMU_MALL_PMFW_CONTROL, NULL);

		if (ret) {

			dev_err(adev->dev, "Init MALL PMFW CONTROL Failure\n");

			return ret;

		}

	} else {

		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_MALLPowerController,

								SMU_MALL_DRIVER_CONTROL, NULL);

		if (ret) {

			dev_err(adev->dev, "Init MALL Driver CONTROL Failure\n");

			return ret;

		}



		if (pg_config == SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON) {

			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_MALLPowerState,

									SMU_MALL_EXIT_PG, NULL);

			if (ret) {

				dev_err(adev->dev, "EXIT MALL PG Failure\n");

				return ret;

			}

		} else if (pg_config == SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_OFF) {

			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_MALLPowerState,

									SMU_MALL_ENTER_PG, NULL);

			if (ret) {

				dev_err(adev->dev, "Enter MALL PG Failure\n");

				return ret;

			}

		}

	}



	return ret;

}



static int smu_v14_0_common_set_mall_enable(struct smu_context *smu)

{

	enum smu_mall_pg_config pg_config = SMU_MALL_PG_CONFIG_DEFAULT;

	int ret = 0;



	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

		ret = smu_v14_0_1_init_mall_power_gating(smu, pg_config);



	return ret;

}



static const struct pptable_funcs smu_v14_0_0_ppt_funcs = {

	.check_fw_status = smu_v14_0_check_fw_status,

	.check_fw_version = smu_v14_0_check_fw_version,
@@ -1454,6 +1526,7 @@ static const struct pptable_funcs smu_v14_0_0_ppt_funcs = { 
	.dpm_set_vpe_enable = smu_v14_0_0_set_vpe_enable,

	.dpm_set_umsch_mm_enable = smu_v14_0_0_set_umsch_mm_enable,

	.get_dpm_clock_table = smu_v14_0_common_get_dpm_table,

	.set_mall_enable = smu_v14_0_common_set_mall_enable,

};



static void smu_v14_0_0_set_smu_mailbox_registers(struct smu_context *smu)