Commit c26ed2ec authored by Mika Kahola's avatar Mika Kahola
Browse files

drm/i915/cx0: Move C20 port clock calculation 



Prepare removal of .clock member from the pll state
structure by moving intel_c20pll_calc_port_clock()
function.

No functional change.

Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-3-mika.kahola@intel.com
parent bc5ecacb

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+50 −50
Original line number Diff line number Diff line
@@ -2130,6 +2130,56 @@ static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, 
	return tmpclk;

}



static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)

{

	return state->tx[0] & C20_PHY_USE_MPLLB;

}



static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,

					const struct intel_c20pll_state *pll_state)

{

	unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;

	unsigned int multiplier, refclk = 38400;

	unsigned int tx_clk_div;

	unsigned int ref_clk_mpllb_div;

	unsigned int fb_clk_div4_en;

	unsigned int ref, vco;

	unsigned int tx_rate_mult;

	unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);



	if (intel_c20phy_use_mpllb(pll_state)) {

		tx_rate_mult = 1;

		frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);

		frac_quot = pll_state->mpllb[8];

		frac_rem =  pll_state->mpllb[9];

		frac_den =  pll_state->mpllb[7];

		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);

		tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);

		ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);

		fb_clk_div4_en = 0;

	} else {

		tx_rate_mult = 2;

		frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);

		frac_quot = pll_state->mplla[8];

		frac_rem =  pll_state->mplla[9];

		frac_den =  pll_state->mplla[7];

		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);

		tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);

		ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);

		fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);

	}



	if (frac_en)

		frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);

	else

		frac = 0;



	ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);

	vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);



	return vco << tx_rate_mult >> tx_clk_div >> tx_rate;

}



/*

 * TODO: Convert the following to align with intel_c20pll_find_table() and

 * intel_c20pll_calc_state_from_table().
@@ -2705,56 +2755,6 @@ int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state, 
	return intel_c20pll_calc_state(crtc_state, encoder, hw_state);

}



static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)

{

	return state->tx[0] & C20_PHY_USE_MPLLB;

}



static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,

					const struct intel_c20pll_state *pll_state)

{

	unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;

	unsigned int multiplier, refclk = 38400;

	unsigned int tx_clk_div;

	unsigned int ref_clk_mpllb_div;

	unsigned int fb_clk_div4_en;

	unsigned int ref, vco;

	unsigned int tx_rate_mult;

	unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);



	if (intel_c20phy_use_mpllb(pll_state)) {

		tx_rate_mult = 1;

		frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);

		frac_quot = pll_state->mpllb[8];

		frac_rem =  pll_state->mpllb[9];

		frac_den =  pll_state->mpllb[7];

		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);

		tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);

		ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);

		fb_clk_div4_en = 0;

	} else {

		tx_rate_mult = 2;

		frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);

		frac_quot = pll_state->mplla[8];

		frac_rem =  pll_state->mplla[9];

		frac_den =  pll_state->mplla[7];

		multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);

		tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);

		ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);

		fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);

	}



	if (frac_en)

		frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);

	else

		frac = 0;



	ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);

	vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);



	return vco << tx_rate_mult >> tx_clk_div >> tx_rate;

}



static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,

					  struct intel_cx0pll_state *cx0pll_state)

{