Commit c2a10081 authored by Minda Chen's avatar Minda Chen Committed by Conor Dooley
Browse files

riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110 



Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC.

Signed-off-by: default avatarMinda Chen <minda.chen@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent f2b539af

arch/riscv/boot/dts/starfive/jh7110.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -446,6 +446,27 @@ i2c2: i2c@10050000 { 
			status = "disabled";

		};



		usbphy0: phy@10200000 {

			compatible = "starfive,jh7110-usb-phy";

			reg = <0x0 0x10200000 0x0 0x10000>;

			clocks = <&syscrg JH7110_SYSCLK_USB_125M>,

				 <&stgcrg JH7110_STGCLK_USB0_APP_125>;

			clock-names = "125m", "app_125m";

			#phy-cells = <0>;

		};



		pciephy0: phy@10210000 {

			compatible = "starfive,jh7110-pcie-phy";

			reg = <0x0 0x10210000 0x0 0x10000>;

			#phy-cells = <0>;

		};



		pciephy1: phy@10220000 {

			compatible = "starfive,jh7110-pcie-phy";

			reg = <0x0 0x10220000 0x0 0x10000>;

			#phy-cells = <0>;

		};



		stgcrg: clock-controller@10230000 {

			compatible = "starfive,jh7110-stgcrg";

			reg = <0x0 0x10230000 0x0 0x10000>;