Unverified Commit c2a60426 authored by Christophe Leroy's avatar Christophe Leroy Committed by Mark Brown
Browse files

soc: fsl: qmc: Only set completion interrupt when needed 



When no post-completion processing is expected, don't waste time
handling useless interrupts.

Only set QMC_BD_[R/T]X_I when a completion function is passed in,
and perform seamless completion on submit for interruptless buffers.

Acked-by: default avatarHerve Codina <herve.codina@bootlin.com>
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Link: https://patch.msgid.link/40b41b53a26e77a50b3a5f68fcecc6f9a40a84b4.1758209158.git.christophe.leroy@csgroup.eu


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f83ec76b

drivers/soc/fsl/qe/qmc.c

+33 −11
Original line number Diff line number Diff line
@@ -461,10 +461,17 @@ int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length, 


	ctrl = qmc_read16(&bd->cbd_sc);

	if (ctrl & (QMC_BD_TX_R | QMC_BD_TX_UB)) {

		if (!(ctrl & (QMC_BD_TX_R | QMC_BD_TX_I)) && bd == chan->txbd_done) {

			if (ctrl & QMC_BD_TX_W)

				chan->txbd_done = chan->txbds;

			else

				chan->txbd_done++;

		} else {

			/* We are full ... */

			ret = -EBUSY;

			goto end;

		}

	}



	qmc_write16(&bd->cbd_datlen, length);

	qmc_write32(&bd->cbd_bufaddr, addr);
@@ -475,6 +482,10 @@ int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length, 


	/* Activate the descriptor */

	ctrl |= (QMC_BD_TX_R | QMC_BD_TX_UB);

	if (complete)

		ctrl |= QMC_BD_TX_I;

	else

		ctrl &= ~QMC_BD_TX_I;

	wmb(); /* Be sure to flush the descriptor before control update */

	qmc_write16(&bd->cbd_sc, ctrl);
@@ -569,10 +580,17 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length, 


	ctrl = qmc_read16(&bd->cbd_sc);

	if (ctrl & (QMC_BD_RX_E | QMC_BD_RX_UB)) {

		if (!(ctrl & (QMC_BD_RX_E | QMC_BD_RX_I)) && bd == chan->rxbd_done) {

			if (ctrl & QMC_BD_RX_W)

				chan->rxbd_done = chan->rxbds;

			else

				chan->rxbd_done++;

		} else {

			/* We are full ... */

			ret = -EBUSY;

			goto end;

		}

	}



	qmc_write16(&bd->cbd_datlen, 0); /* data length is updated by the QMC */

	qmc_write32(&bd->cbd_bufaddr, addr);
@@ -587,6 +605,10 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length, 


	/* Activate the descriptor */

	ctrl |= (QMC_BD_RX_E | QMC_BD_RX_UB);

	if (complete)

		ctrl |= QMC_BD_RX_I;

	else

		ctrl &= ~QMC_BD_RX_I;

	wmb(); /* Be sure to flush data before descriptor activation */

	qmc_write16(&bd->cbd_sc, ctrl);
@@ -1482,19 +1504,19 @@ static int qmc_setup_chan(struct qmc *qmc, struct qmc_chan *chan) 


	/* Init Rx BDs and set Wrap bit on last descriptor */

	BUILD_BUG_ON(QMC_NB_RXBDS == 0);

	val = QMC_BD_RX_I;

	for (i = 0; i < QMC_NB_RXBDS; i++) {

		bd = chan->rxbds + i;

		qmc_write16(&bd->cbd_sc, val);

		qmc_write16(&bd->cbd_sc, 0);

	}

	bd = chan->rxbds + QMC_NB_RXBDS - 1;

	qmc_write16(&bd->cbd_sc, val | QMC_BD_RX_W);

	qmc_write16(&bd->cbd_sc, QMC_BD_RX_W);



	/* Init Tx BDs and set Wrap bit on last descriptor */

	BUILD_BUG_ON(QMC_NB_TXBDS == 0);

	val = QMC_BD_TX_I;

	if (chan->mode == QMC_HDLC)

		val |= QMC_BD_TX_L | QMC_BD_TX_TC;

		val = QMC_BD_TX_L | QMC_BD_TX_TC;

	else

		val = 0;

	for (i = 0; i < QMC_NB_TXBDS; i++) {

		bd = chan->txbds + i;

		qmc_write16(&bd->cbd_sc, val);