Commit c3040662 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: remove a function that does complex calculation in every frame but not used 



[why]
The result of predict_pipe_split calculation is no longer used but the
function is not removed. This will cause unnecessary calculation
of pipe split prediction in every frame update.

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e379162a

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+0 −3
Original line number Diff line number Diff line
@@ -2031,9 +2031,6 @@ int dcn32_populate_dml_pipes_from_context( 
			}

		}



		DC_FP_START();

		dcn32_predict_pipe_split(context, &pipes[pipe_cnt]);

		DC_FP_END();



		pipe_cnt++;

	}

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+0 −84
Original line number Diff line number Diff line
@@ -348,90 +348,6 @@ void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, 
	}

}



/**

 * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML pipe

 * @context: [in] New DC state to be programmed

 * @pipe_e2e: [in] DML pipe end to end context

 *

 * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is required (both

 * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode, and MPC combine is

 * determined by DPPClk requirements

 *

 * This function follows the same policy as DML:

 * - Check for ODM combine requirements / policy first

 * - MPC combine is only chosen if there is no ODM combine requirements / policy in place, and

 *   MPC is required

 *

 * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for no splits).

 */

uint8_t dcn32_predict_pipe_split(struct dc_state *context,

				  display_e2e_pipe_params_st *pipe_e2e)

{

	double pscl_throughput;

	double pscl_throughput_chroma;

	double dpp_clk_single_dpp, clock;

	double clk_frequency = 0.0;

	double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz;

	bool total_available_pipes_support = false;

	uint32_t number_of_dpp = 0;

	enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled;

	double req_dispclk_per_surface = 0;

	uint8_t num_splits = 0;



	dc_assert_fp_enabled();



	dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit,

			pipe_e2e->pipe.dest.hactive,

			pipe_e2e->dout.output_format,

			pipe_e2e->dout.output_type,

			pipe_e2e->pipe.dest.odm_combine_policy,

			context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,

			context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,

			pipe_e2e->dout.dsc_enable != 0,

			0, /* TotalNumberOfActiveDPP can be 0 since we're predicting pipe split requirement */

			context->bw_ctx.dml.ip.max_num_dpp,

			pipe_e2e->pipe.dest.pixel_rate_mhz,

			context->bw_ctx.dml.soc.dcn_downspread_percent,

			context->bw_ctx.dml.ip.dispclk_ramp_margin_percent,

			context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz,

			pipe_e2e->dout.dsc_slices,

			/* Output */

			&total_available_pipes_support,

			&number_of_dpp,

			&odm_mode,

			&req_dispclk_per_surface);



	dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio,

			pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c,

			pipe_e2e->pipe.scale_ratio_depth.vscl_ratio,

			pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c,

			context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk,

			context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk,

			pipe_e2e->pipe.dest.pixel_rate_mhz,

			pipe_e2e->pipe.src.source_format,

			pipe_e2e->pipe.scale_taps.htaps,

			pipe_e2e->pipe.scale_taps.htaps_c,

			pipe_e2e->pipe.scale_taps.vtaps,

			pipe_e2e->pipe.scale_taps.vtaps_c,

			/* Output */

			&pscl_throughput, &pscl_throughput_chroma,

			&dpp_clk_single_dpp);



	clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100);



	if (clock > 0)

		clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0) / clock);



	if (odm_mode == dm_odm_combine_mode_2to1)

		num_splits = 1;

	else if (odm_mode == dm_odm_combine_mode_4to1)

		num_splits = 3;

	else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz)

		num_splits = 1;



	return num_splits;

}



static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)

{

	float memory_bw_kbytes_sec;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

+0 −3
Original line number Diff line number Diff line
@@ -36,9 +36,6 @@ void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, 
					      display_e2e_pipe_params_st *pipes,

					      int pipe_cnt);



uint8_t dcn32_predict_pipe_split(struct dc_state *context,

				  display_e2e_pipe_params_st *pipe_e2e);



void dcn32_set_phantom_stream_timing(struct dc *dc,

				     struct dc_state *context,

				     struct pipe_ctx *ref_pipe,