Commit c32f4f4a authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Bjorn Andersson
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clk: qcom: clk-alpha-pll: Add support for zonda ole pll configure 



Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add
support for it.

Signed-off-by: default avatarRajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-6-7fb08c861c7c@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 78654850

drivers/clk/qcom/clk-alpha-pll.c

+16 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
#define PLL_CONFIG_CTL(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])

#define PLL_CONFIG_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])

#define PLL_CONFIG_CTL_U1(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])

#define PLL_CONFIG_CTL_U2(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])

#define PLL_TEST_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])

#define PLL_TEST_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])

#define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
@@ -228,6 +229,21 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_ALPHA_VAL] = 0x24,

		[PLL_OFF_ALPHA_VAL_U] = 0x28,

	},

	[CLK_ALPHA_PLL_TYPE_ZONDA_OLE] =  {

		[PLL_OFF_L_VAL] = 0x04,

		[PLL_OFF_ALPHA_VAL] = 0x08,

		[PLL_OFF_USER_CTL] = 0x0c,

		[PLL_OFF_USER_CTL_U] = 0x10,

		[PLL_OFF_CONFIG_CTL] = 0x14,

		[PLL_OFF_CONFIG_CTL_U] = 0x18,

		[PLL_OFF_CONFIG_CTL_U1] = 0x1c,

		[PLL_OFF_CONFIG_CTL_U2] = 0x20,

		[PLL_OFF_TEST_CTL] = 0x24,

		[PLL_OFF_TEST_CTL_U] = 0x28,

		[PLL_OFF_TEST_CTL_U1] = 0x2c,

		[PLL_OFF_OPMODE] = 0x30,

		[PLL_OFF_STATUS] = 0x3c,

	},

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);

drivers/clk/qcom/clk-alpha-pll.h

+4 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ enum { 
	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,

	CLK_ALPHA_PLL_TYPE_AGERA,

	CLK_ALPHA_PLL_TYPE_ZONDA,

	CLK_ALPHA_PLL_TYPE_ZONDA_OLE,

	CLK_ALPHA_PLL_TYPE_LUCID_EVO,

	CLK_ALPHA_PLL_TYPE_LUCID_OLE,

	CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
@@ -42,6 +43,7 @@ enum { 
	PLL_OFF_CONFIG_CTL,

	PLL_OFF_CONFIG_CTL_U,

	PLL_OFF_CONFIG_CTL_U1,

	PLL_OFF_CONFIG_CTL_U2,

	PLL_OFF_TEST_CTL,

	PLL_OFF_TEST_CTL_U,

	PLL_OFF_TEST_CTL_U1,
@@ -119,6 +121,7 @@ struct alpha_pll_config { 
	u32 config_ctl_val;

	u32 config_ctl_hi_val;

	u32 config_ctl_hi1_val;

	u32 config_ctl_hi2_val;

	u32 user_ctl_val;

	u32 user_ctl_hi_val;

	u32 user_ctl_hi1_val;
@@ -173,6 +176,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; 


extern const struct clk_ops clk_alpha_pll_zonda_ops;

#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops

#define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops



extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;

extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;