Commit c33ffdb7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy updates from Vinod Koul:
 "New Support
   - Samsung Exynos gs101 drd combo phy
   - Qualcomm SC8180x USB uniphy, IPQ9574 QMP PCIe phy
   - Airoha EN7581 PCIe phy
   - Freescale i.MX8Q HSIO SerDes phy
   - Starfive jh7110 dphy tx

  Updates:
   - Resume support for j721e-wiz driver
   - Updates to Exynos usbdrd driver
   - Support for optional power domains in g12a usb2-phy driver
   - Debugfs support and updates to zynqmp driver"

* tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (56 commits)
  phy: airoha: Add dtime and Rx AEQ IO registers
  dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers
  dt-bindings: phy: rockchip-emmc-phy: Convert to dtschema
  dt-bindings: phy: qcom,qmp-usb: fix spelling error
  phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)
  phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk
  phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
  phy: exynos5-usbdrd: convert core clocks to clk_bulk
  phy: exynos5-usbdrd: support isolating HS and SS ports independently
  dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible
  phy: core: Fix documentation of of_phy_get
  phy: starfive: Correct the dphy configure process
  phy: zynqmp: Add debugfs support
  phy: zynqmp: Take the phy mutex in xlate
  phy: zynqmp: Only wait for PLL lock "primary" instances
  phy: zynqmp: Store instance instead of type
  phy: zynqmp: Enable reference clock correctly
  phy: cadence-torrent: Check return value on register read
  phy: Fix the cacography in phy-exynos5250-usb2.c
  phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCON
  ...
parents ad7b0b7b 2a011c3c

Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Airoha EN7581 PCI-Express PHY



maintainers:

  - Lorenzo Bianconi <lorenzo@kernel.org>



description:

  The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.



properties:

  compatible:

    const: airoha,en7581-pcie-phy



  reg:

    items:

      - description: PCIE analog base address

      - description: PCIE lane0 base address

      - description: PCIE lane1 base address

      - description: PCIE lane0 detection time base address

      - description: PCIE lane1 detection time base address

      - description: PCIE Rx AEQ base address



  reg-names:

    items:

      - const: csr-2l

      - const: pma0

      - const: pma1

      - const: p0-xr-dtime

      - const: p1-xr-dtime

      - const: rx-aeq



  "#phy-cells":

    const: 0



required:

  - compatible

  - reg

  - reg-names

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/phy/phy.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        phy@11e80000 {

            compatible = "airoha,en7581-pcie-phy";

            #phy-cells = <0>;

            reg = <0x0 0x1fa5a000 0x0 0xfff>,

                  <0x0 0x1fa5b000 0x0 0xfff>,

                  <0x0 0x1fa5c000 0x0 0xfff>,

                  <0x0 0x1fc10044 0x0 0x4>,

                  <0x0 0x1fc30044 0x0 0x4>,

                  <0x0 0x1fc15030 0x0 0x104>;

            reg-names = "csr-2l", "pma0", "pma1",

                        "p0-xr-dtime", "p1-xr-dtime",

                        "rx-aeq";

        };

    };

Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml

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@@ -41,6 +41,9 @@ properties: 
      Phandle to a regulator that provides power to the PHY. This

      regulator will be managed during the PHY power on/off sequence.



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY



maintainers:

  - Richard Zhu <hongxing.zhu@nxp.com>



properties:

  compatible:

    enum:

      - fsl,imx8qm-hsio

      - fsl,imx8qxp-hsio

  reg:

    items:

      - description: Base address and length of the PHY block

      - description: HSIO control and status registers(CSR) of the PHY

      - description: HSIO CSR of the controller bound to the PHY

      - description: HSIO CSR for MISC



  reg-names:

    items:

      - const: reg

      - const: phy

      - const: ctrl

      - const: misc



  "#phy-cells":

    const: 3

    description:

      The first defines lane index.

      The second defines the type of the PHY refer to the include phy.h.

      The third defines the controller index, indicated which controller

      is bound to the lane.



  clocks:

    minItems: 5

    maxItems: 14



  clock-names:

    minItems: 5

    maxItems: 14



  fsl,hsio-cfg:

    description: |

      Specifies the use case of the HSIO module in the hardware design.

      Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be

      confiured as following three use cases.

      +---------------------------------------+

      |                  | i.MX8QM            |

      |------------------|--------------------|

      |                  | Lane0| Lane1| Lane2|

      |------------------|------|------|------|

      | pciea-x2-sata    | PCIEA| PCIEA| SATA |

      |------------------|------|------|------|

      | pciea-x2-pcieb   | PCIEA| PCIEA| PCIEB|

      |------------------|------|------|------|

      | pciea-pcieb-sata | PCIEA| PCIEB| SATA |

      +---------------------------------------+

    $ref: /schemas/types.yaml#/definitions/string

    enum: [ pciea-x2-sata, pciea-x2-pcieb, pciea-pcieb-sata]

    default: pciea-pcieb-sata



  fsl,refclk-pad-mode:

    description:

      Specifies the mode of the refclk pad used. INPUT(PHY refclock is

      provided externally via the refclk pad) or OUTPUT(PHY refclock is

      derived from SoC internal source and provided on the refclk pad).

      This property not exists means unused(PHY refclock is derived from

      SoC internal source).

    $ref: /schemas/types.yaml#/definitions/string

    enum: [ input, output, unused ]

    default: unused



  power-domains:

    minItems: 1

    maxItems: 2



required:

  - compatible

  - reg

  - reg-names

  - "#phy-cells"

  - clocks

  - clock-names

  - fsl,hsio-cfg



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8qxp-hsio

    then:

      properties:

        clock-names:

          items:

            - const: pclk0

            - const: apb_pclk0

            - const: phy0_crr

            - const: ctl0_crr

            - const: misc_crr

        power-domains:

          maxItems: 1



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8qm-hsio

    then:

      properties:

        clock-names:

          items:

            - const: pclk0

            - const: pclk1

            - const: apb_pclk0

            - const: apb_pclk1

            - const: pclk2

            - const: epcs_tx

            - const: epcs_rx

            - const: apb_pclk2

            - const: phy0_crr

            - const: phy1_crr

            - const: ctl0_crr

            - const: ctl1_crr

            - const: ctl2_crr

            - const: misc_crr

        power-domains:

          minItems: 2



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8-clock.h>

    #include <dt-bindings/clock/imx8-lpcg.h>

    #include <dt-bindings/firmware/imx/rsrc.h>

    #include <dt-bindings/phy/phy-imx8-pcie.h>



    phy@5f1a0000 {

        compatible = "fsl,imx8qxp-hsio";

        reg = <0x5f1a0000 0x10000>,

              <0x5f120000 0x10000>,

              <0x5f140000 0x10000>,

              <0x5f160000 0x10000>;

        reg-names = "reg", "phy", "ctrl", "misc";

        clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,

                 <&phyx1_lpcg IMX_LPCG_CLK_4>,

                 <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,

                 <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,

                 <&misc_crr5_lpcg IMX_LPCG_CLK_4>;

        clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", "misc_crr";

        power-domains = <&pd IMX_SC_R_SERDES_1>;

        #phy-cells = <3>;

        fsl,hsio-cfg = "pciea-pcieb-sata";

        fsl,refclk-pad-mode = "input";

    };

...

Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml

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@@ -41,6 +41,12 @@ properties: 
      Phandle to the system controller node

    $ref: /schemas/types.yaml#/definitions/phandle



  swap-dx-lanes:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    description: |

      Specifies the ports which will swap the differential-pair (D+/D-),

      default is not-swapped.



# Required child nodes:



patternProperties:

Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml

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@@ -19,6 +19,8 @@ properties: 
      - qcom,ipq6018-qmp-pcie-phy

      - qcom,ipq8074-qmp-gen3-pcie-phy

      - qcom,ipq8074-qmp-pcie-phy

      - qcom,ipq9574-qmp-gen3x1-pcie-phy

      - qcom,ipq9574-qmp-gen3x2-pcie-phy



  reg:

    items: