Unverified Commit c3aa8c72 authored by Nuno Sá's avatar Nuno Sá Committed by Stephen Boyd
Browse files

clk: clk-axi-clkgen: fix coding style issues 



This is just cosmetics and so no functional changes intended.

While at it, sort header in alphabetical order.

Signed-off-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-7-bc4b3b61d1d4@analog.com


Reviewed-by: default avatarDavid Lechner <dlechner@baylibre.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 34e42e9a

drivers/clk/clk-axi-clkgen.c

+41 −40
Original line number Diff line number Diff line
@@ -8,15 +8,15 @@ 


#include <linux/adi-axi-common.h>

#include <linux/bits.h>

#include <linux/platform_device.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/slab.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/module.h>

#include <linux/mod_devicetable.h>

#include <linux/err.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/slab.h>



#define AXI_CLKGEN_V2_REG_RESET		0x40

#define AXI_CLKGEN_V2_REG_CLKSEL	0x44
@@ -96,7 +96,7 @@ static uint32_t axi_clkgen_lookup_filter(unsigned int m) 
	}

}



static const uint32_t axi_clkgen_lock_table[] = {

static const u32 axi_clkgen_lock_table[] = {

	0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,

	0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,

	0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
@@ -108,7 +108,7 @@ static const uint32_t axi_clkgen_lock_table[] = { 
	0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,

};



static uint32_t axi_clkgen_lookup_lock(unsigned int m)

static u32 axi_clkgen_lookup_lock(unsigned int m)

{

	if (m < ARRAY_SIZE(axi_clkgen_lock_table))

		return axi_clkgen_lock_table[m];
@@ -131,7 +131,8 @@ static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { 


static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,

				   unsigned long fin, unsigned long fout,

	unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)

				   unsigned int *best_d, unsigned int *best_m,

				   unsigned int *best_dout)

{

	unsigned long d, d_min, d_max, _d_min, _d_max;

	unsigned long m, m_min, m_max;
@@ -198,9 +199,9 @@ struct axi_clkgen_div_params { 
};



static void axi_clkgen_calc_clk_params(unsigned int divider,

	unsigned int frac_divider, struct axi_clkgen_div_params *params)

				       unsigned int frac_divider,

				       struct axi_clkgen_div_params *params)

{



	memset(params, 0x0, sizeof(*params));



	if (divider == 1) {
@@ -287,7 +288,8 @@ static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, 
}



static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,

	unsigned int reg, unsigned int val, unsigned int mask)

				 unsigned int reg, unsigned int val,

				 unsigned int mask)

{

	unsigned int reg_val = 0;

	int ret;
@@ -308,8 +310,7 @@ static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, 
	return 0;

}



static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,

	bool enable)

static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, bool enable)

{

	unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
@@ -325,7 +326,8 @@ static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw) 
}



static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,

	unsigned int reg1, unsigned int reg2, unsigned int reg3,

			       unsigned int reg1, unsigned int reg2,

			       unsigned int reg3,

			       struct axi_clkgen_div_params *params)

{

	axi_clkgen_mmcm_write(axi_clkgen, reg1,
@@ -336,20 +338,19 @@ static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen, 
			      (params->nocount << 6), 0x7fff);

	if (reg3 != 0) {

		axi_clkgen_mmcm_write(axi_clkgen, reg3,

			(params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);

				      (params->frac_phase << 11) | (params->frac_wf_f << 10),

				      0x3c00);

	}

}



static int axi_clkgen_set_rate(struct clk_hw *clk_hw,

	unsigned long rate, unsigned long parent_rate)

static int axi_clkgen_set_rate(struct clk_hw *clk_hw, unsigned long rate,

			       unsigned long parent_rate)

{

	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);

	const struct axi_clkgen_limits *limits = &axi_clkgen->limits;

	unsigned int d, m, dout;

	struct axi_clkgen_div_params params;

	uint32_t power = 0;

	uint32_t filter;

	uint32_t lock;

	u32 power = 0, filter, lock;



	if (parent_rate == 0 || rate == 0)

		return -EINVAL;