Commit c3bec954 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a779h0: Fix IRQ suffixes 



The suffixes of the IRQ identifiers, as used for pins related to the
Interrupt Controller for External Devices (INTC-EX), are inconsistent.
Correct them to match the Pin Multiplex attachment in Rev.0.51 of the
R-Car V4M Series Hardware User's Manual.

Fixes: 291f7856 ("pinctrl: renesas: Initial R8A779H0 (R-Car V4M) PFC support")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7d3c7498d9e8eda5583b15f9163eb25bb797ed24.1713282028.git.geert+renesas@glider.be
parent 2487dc87

drivers/pinctrl/renesas/pfc-r8a779h0.c

+12 −12
Original line number Diff line number Diff line
@@ -75,10 +75,10 @@ 
#define GPSR0_9		F_(MSIOF5_SYNC,		IP1SR0_7_4)

#define GPSR0_8		F_(MSIOF5_SS1,		IP1SR0_3_0)

#define GPSR0_7		F_(MSIOF5_SS2,		IP0SR0_31_28)

#define GPSR0_6		F_(IRQ0,		IP0SR0_27_24)

#define GPSR0_5		F_(IRQ1,		IP0SR0_23_20)

#define GPSR0_4		F_(IRQ2,		IP0SR0_19_16)

#define GPSR0_3		F_(IRQ3,		IP0SR0_15_12)

#define GPSR0_6		F_(IRQ0_A,		IP0SR0_27_24)

#define GPSR0_5		F_(IRQ1_A,		IP0SR0_23_20)

#define GPSR0_4		F_(IRQ2_A,		IP0SR0_19_16)

#define GPSR0_3		F_(IRQ3_A,		IP0SR0_15_12)

#define GPSR0_2		F_(GP0_02,		IP0SR0_11_8)

#define GPSR0_1		F_(GP0_01,		IP0SR0_7_4)

#define GPSR0_0		F_(GP0_00,		IP0SR0_3_0)
@@ -265,10 +265,10 @@ 
#define IP0SR0_3_0	F_(0, 0)		FM(ERROROUTC_N_B)	FM(TCLK2_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_7_4	F_(0, 0)		FM(MSIOF3_SS1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_11_8	F_(0, 0)		FM(MSIOF3_SS2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_15_12	FM(IRQ3)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_19_16	FM(IRQ2)		FM(MSIOF3_TXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_23_20	FM(IRQ1)		FM(MSIOF3_RXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_27_24	FM(IRQ0)		FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_15_12	FM(IRQ3_A)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_19_16	FM(IRQ2_A)		FM(MSIOF3_TXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_23_20	FM(IRQ1_A)		FM(MSIOF3_RXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_27_24	FM(IRQ0_A)		FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_31_28	FM(MSIOF5_SS2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)



/* IP1SR0 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
@@ -672,16 +672,16 @@ static const u16 pinmux_data[] = { 


	PINMUX_IPSR_GPSR(IP0SR0_11_8,	MSIOF3_SS2),



	PINMUX_IPSR_GPSR(IP0SR0_15_12,	IRQ3),

	PINMUX_IPSR_GPSR(IP0SR0_15_12,	IRQ3_A),

	PINMUX_IPSR_GPSR(IP0SR0_15_12,	MSIOF3_SCK),



	PINMUX_IPSR_GPSR(IP0SR0_19_16,	IRQ2),

	PINMUX_IPSR_GPSR(IP0SR0_19_16,	IRQ2_A),

	PINMUX_IPSR_GPSR(IP0SR0_19_16,	MSIOF3_TXD),



	PINMUX_IPSR_GPSR(IP0SR0_23_20,	IRQ1),

	PINMUX_IPSR_GPSR(IP0SR0_23_20,	IRQ1_A),

	PINMUX_IPSR_GPSR(IP0SR0_23_20,	MSIOF3_RXD),



	PINMUX_IPSR_GPSR(IP0SR0_27_24,	IRQ0),

	PINMUX_IPSR_GPSR(IP0SR0_27_24,	IRQ0_A),

	PINMUX_IPSR_GPSR(IP0SR0_27_24,	MSIOF3_SYNC),



	PINMUX_IPSR_GPSR(IP0SR0_31_28,	MSIOF5_SS2),