Commit c3c6ab95 authored by Arkadiusz Kubalewski's avatar Arkadiusz Kubalewski Committed by David S. Miller
Browse files

dpll: spec: add support for pin-dpll signal phase offset/adjust 



Add attributes for providing the user with:
- measurement of signals phase offset between pin and dpll
- ability to adjust the phase of pin signal

Signed-off-by: default avatarArkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 27ed30d1

Documentation/netlink/specs/dpll.yaml

+30 −0
Original line number Diff line number Diff line
@@ -164,6 +164,18 @@ definitions: 
      -

        name: state-can-change

        doc: pin state can be changed

  -

    type: const

    name: phase-offset-divider

    value: 1000

    doc: |

      phase offset divider allows userspace to calculate a value of

      measured signal phase difference between a pin and dpll device

      as a fractional value with three digit decimal precision.

      Value of (DPLL_A_PHASE_OFFSET / DPLL_PHASE_OFFSET_DIVIDER) is an

      integer part of a measured phase offset value.

      Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a

      fractional part of a measured phase offset value.



attribute-sets:

  -
@@ -272,6 +284,18 @@ attribute-sets: 
        type: nest

        multi-attr: true

        nested-attributes: pin-parent-pin

      -

        name: phase-adjust-min

        type: s32

      -

        name: phase-adjust-max

        type: s32

      -

        name: phase-adjust

        type: s32

      -

        name: phase-offset

        type: s64

  -

    name: pin-parent-device

    subset-of: pin
@@ -284,6 +308,8 @@ attribute-sets: 
        name: prio

      -

        name: state

      -

        name: phase-offset

  -

    name: pin-parent-pin

    subset-of: pin
@@ -431,6 +457,9 @@ operations: 
            - capabilities

            - parent-device

            - parent-pin

            - phase-adjust-min

            - phase-adjust-max

            - phase-adjust



      dump:

        pre: dpll-lock-dumpit
@@ -458,6 +487,7 @@ operations: 
            - state

            - parent-device

            - parent-pin

            - phase-adjust

    -

      name: pin-create-ntf

      doc: Notification about pin appearing

drivers/dpll/dpll_nl.c

+5 −3
Original line number Diff line number Diff line
@@ -11,11 +11,12 @@ 
#include <uapi/linux/dpll.h>



/* Common nested types */

const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1] = {

const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1] = {

	[DPLL_A_PIN_PARENT_ID] = { .type = NLA_U32, },

	[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),

	[DPLL_A_PIN_PRIO] = { .type = NLA_U32, },

	[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),

	[DPLL_A_PIN_PHASE_OFFSET] = { .type = NLA_S64, },

};



const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = {
@@ -61,7 +62,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_policy[DPLL_A_PIN_ID + 1] = 
};



/* DPLL_CMD_PIN_SET - do */

static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1] = {

static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PHASE_ADJUST + 1] = {

	[DPLL_A_PIN_ID] = { .type = NLA_U32, },

	[DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, },

	[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
@@ -69,6 +70,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1] 
	[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),

	[DPLL_A_PIN_PARENT_DEVICE] = NLA_POLICY_NESTED(dpll_pin_parent_device_nl_policy),

	[DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy),

	[DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, },

};



/* Ops table for dpll */
@@ -140,7 +142,7 @@ static const struct genl_split_ops dpll_nl_ops[] = { 
		.doit		= dpll_nl_pin_set_doit,

		.post_doit	= dpll_pin_post_doit,

		.policy		= dpll_pin_set_nl_policy,

		.maxattr	= DPLL_A_PIN_PARENT_PIN,

		.maxattr	= DPLL_A_PIN_PHASE_ADJUST,

		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DO,

	},

};

drivers/dpll/dpll_nl.h

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#include <uapi/linux/dpll.h>



/* Common nested types */

extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1];

extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1];

extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1];



int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb,

include/uapi/linux/dpll.h

+6 −0
Original line number Diff line number Diff line
@@ -138,6 +138,8 @@ enum dpll_pin_capabilities { 
	DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,

};



#define DPLL_PHASE_OFFSET_DIVIDER	1000



enum dpll_a {

	DPLL_A_ID = 1,

	DPLL_A_MODULE_NAME,
@@ -173,6 +175,10 @@ enum dpll_a_pin { 
	DPLL_A_PIN_CAPABILITIES,

	DPLL_A_PIN_PARENT_DEVICE,

	DPLL_A_PIN_PARENT_PIN,

	DPLL_A_PIN_PHASE_ADJUST_MIN,

	DPLL_A_PIN_PHASE_ADJUST_MAX,

	DPLL_A_PIN_PHASE_ADJUST,

	DPLL_A_PIN_PHASE_OFFSET,



	__DPLL_A_PIN_MAX,

	DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)