Commit c3fe7071 authored by Valmantas Paliksa's avatar Valmantas Paliksa Committed by Vinod Koul
Browse files

phy: rockchip-pcie: Enable all four lanes if required 



Current code enables only Lane 0 because pwr_cnt will be incremented on
first call to the function. Let's reorder the enablement code to enable
all 4 lanes through GRF.

Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: default avatarRobin Murphy <robin.murphy@arm.com>

Signed-off-by: default avatarValmantas Paliksa <walmis@gmail.com>
Signed-off-by: default avatarGeraldo Nascimento <geraldogabriel@gmail.com>
Reviewed-by: default avatarRobin Murphy <robin.murphy@arm.com>
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/16b610aab34e069fd31d9f57260c10df2a968f80.1751322015.git.geraldogabriel@gmail.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent dfef90f2

drivers/phy/rockchip/phy-rockchip-pcie.c

+6 −6
Original line number Diff line number Diff line
@@ -160,6 +160,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) 


	guard(mutex)(&rk_phy->pcie_mutex);



	regmap_write(rk_phy->reg_base,

		     rk_phy->phy_data->pcie_laneoff,

		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,

				   PHY_LANE_IDLE_MASK,

				   PHY_LANE_IDLE_A_SHIFT + inst->index));



	if (rk_phy->pwr_cnt++) {

		return 0;

	}
@@ -176,12 +182,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) 
				   PHY_CFG_ADDR_MASK,

				   PHY_CFG_ADDR_SHIFT));



	regmap_write(rk_phy->reg_base,

		     rk_phy->phy_data->pcie_laneoff,

		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,

				   PHY_LANE_IDLE_MASK,

				   PHY_LANE_IDLE_A_SHIFT + inst->index));



	/*

	 * No documented timeout value for phy operation below,

	 * so we make it large enough here. And we use loop-break