Commit c434e25b authored Jul 19, 2024 by Linus Torvalds

Merge tag 'v6.11-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

Pull crypto update from Herbert Xu:
 "API:
   - Test setkey in no-SIMD context
   - Add skcipher speed test for user-specified algorithm

  Algorithms:
   - Add x25519 support on ppc64le
   - Add VAES and AVX512 / AVX10 optimized AES-GCM on x86
   - Remove sm2 algorithm

  Drivers:
   - Add Allwinner H616 support to sun8i-ce
   - Use DMA in stm32
   - Add Exynos850 hwrng support to exynos"

* tag 'v6.11-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (81 commits)
  hwrng: core - remove (un)register_miscdev()
  crypto: lib/mpi - delete unnecessary condition
  crypto: testmgr - generate power-of-2 lengths more often
  crypto: mxs-dcp - Ensure payload is zero when using key slot
  hwrng: Kconfig - Do not enable by default CN10K driver
  crypto: starfive - Fix nent assignment in rsa dec
  crypto: starfive - Align rsa input data to 32-bit
  crypto: qat - fix unintentional re-enabling of error interrupts
  crypto: qat - extend scope of lock in adf_cfg_add_key_value_param()
  Documentation: qat: fix auto_reset attribute details
  crypto: sun8i-ce - add Allwinner H616 support
  crypto: sun8i-ce - wrap accesses to descriptor address fields
  dt-bindings: crypto: sun8i-ce: Add compatible for H616
  hwrng: core - Fix wrong quality calculation at hw rng registration
  hwrng: exynos - Enable Exynos850 support
  hwrng: exynos - Add SMC based TRNG operation
  hwrng: exynos - Implement bus clock control
  hwrng: exynos - Use devm_clk_get_enabled() to get the clock
  hwrng: exynos - Improve coding style
  dt-bindings: rng: Add Exynos850 support to exynos-trng
  ...

parents 720261cf df1e9791

Documentation/ABI/testing/sysfs-driver-qat

+2 −2

Original line number	Diff line number	Diff line
		@@ -143,8 +143,8 @@ Description:
		This attribute is only available for qat_4xxx devices.

		What: /sys/bus/pci/devices/<BDF>/qat/auto_reset
		Date: March 2024
		KernelVersion: 6.8
		Date: May 2024
		KernelVersion: 6.9
		Contact: qat-linux@intel.com
		Description: (RW) Reports the current state of the autoreset feature
		for a QAT device

Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml

+2 −0

Original line number	Diff line number	Diff line
		@@ -18,6 +18,7 @@ properties:
		- allwinner,sun50i-a64-crypto
		- allwinner,sun50i-h5-crypto
		- allwinner,sun50i-h6-crypto
		- allwinner,sun50i-h616-crypto

		reg:
		maxItems: 1
		@@ -49,6 +50,7 @@ if:
		compatible:
		enum:
		- allwinner,sun20i-d1-crypto
		- allwinner,sun50i-h616-crypto
		then:
		properties:
		clocks:

Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml

+3 −0

Original line number	Diff line number	Diff line
		@@ -26,6 +26,9 @@ properties:
		items:
		- const: core

		power-domains:
		maxItems: 1

		required:
		- compatible
		- reg

Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml

+36 −4

Original line number	Diff line number	Diff line
		@@ -12,14 +12,17 @@ maintainers:

		properties:
		compatible:
		const: samsung,exynos5250-trng
		enum:
		- samsung,exynos5250-trng
		- samsung,exynos850-trng

		clocks:
		maxItems: 1
		minItems: 1
		maxItems: 2

		clock-names:
		items:
		- const: secss
		minItems: 1
		maxItems: 2

		reg:
		maxItems: 1
		@@ -30,6 +33,35 @@ required:
		- clock-names
		- reg

		allOf:
		- if:
		properties:
		compatible:
		contains:
		const: samsung,exynos850-trng

		then:
		properties:
		clocks:
		items:
		- description: SSS (Security Sub System) operating clock
		- description: SSS (Security Sub System) bus clock

		clock-names:
		items:
		- const: secss
		- const: pclk

		else:
		properties:
		clocks:
		items:
		- description: SSS (Security Sub System) operating clock

		clock-names:
		items:
		- const: secss

		additionalProperties: false

		examples:

MAINTAINERS

+6 −0

Original line number	Diff line number	Diff line
		@@ -980,6 +980,12 @@ F: include/uapi/linux/psp-dbc.h
		F: tools/crypto/ccp/*.c
		F: tools/crypto/ccp/*.py

		AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - HSTI SUPPORT
		M: Mario Limonciello <mario.limonciello@amd.com>
		L: linux-crypto@vger.kernel.org
		S: Supported
		F: drivers/crypto/ccp/hsti.*

		AMD DISPLAY CORE
		M: Harry Wentland <harry.wentland@amd.com>
		M: Leo Li <sunpeng.li@amd.com>