Commit c460535a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2025-07-18-1' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Seems like a quiet enough week, xe/amdgpu being the usual suspects,
  then mediatek with a few fixes, and otherwise just misc other bits.

  dp:
   - aux dpcd address fix

  xe:
   - SR-IOV fixes for GT reset and TLB invalidation
   - Fix memory copy direction during migration
   - Fix alignment check on migration
   - Fix MOCS and page fault init order to correctly account
     for topology

  amdgpu:
   - Fix a DC memory leak
   - DCN 4.0.1 degamma LUT fix
   - Fix reset counter handling for soft recovery
   - GC 8 fix

  radeon:
   - Drop console locks when suspending/resuming

  nouveau:
   - ioctl validation fix

  panfrost:
   - scheduler bug fix

  mediatek:
   - Add wait_event_timeout when disabling plane
   - only announce AFBC if really supported
   - mtk_dpi: Reorder output formats on MT8195/88"

* tag 'drm-fixes-2025-07-18-1' of https://gitlab.freedesktop.org/drm/kernel:
  drm/mediatek: mtk_dpi: Reorder output formats on MT8195/88
  drm/mediatek: only announce AFBC if really supported
  drm/mediatek: Add wait_event_timeout when disabling plane
  drm/xe/pf: Resend PF provisioning after GT reset
  drm/xe/pf: Prepare to stop SR-IOV support prior GT reset
  drm/xe/migrate: Fix alignment check
  drm/xe: Move page fault init after topology init
  drm/xe/mocs: Initialize MOCS index early
  drm/xe/migrate: fix copy direction in access_memory
  drm/xe: Dont skip TLB invalidations on VF
  drm/amdgpu/gfx8: reset compute ring wptr on the GPU on resume
  drm/amdgpu: Increase reset counter only on success
  drm/radeon: Do not hold console lock during resume
  drm/radeon: Do not hold console lock while suspending clients
  drm/amd/display: Disable CRTC degamma LUT for DCN401
  drm/amd/display: Free memory allocation
  drm/dp: Change AUX DPCD probe address from LANE0_1_STATUS to TRAINING_PATTERN_SET
  drm/panfrost: Fix scheduler workqueue bug
  drm/nouveau: check ioctl command codes better
parents f0afb7bd 4d33ed64

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

+7 −2
Original line number Diff line number Diff line
@@ -427,6 +427,7 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 
{

	unsigned long flags;

	ktime_t deadline;

	bool ret;



	if (unlikely(ring->adev->debug_disable_soft_recovery))

		return false;
@@ -441,12 +442,16 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 
		dma_fence_set_error(fence, -ENODATA);

	spin_unlock_irqrestore(fence->lock, flags);



	atomic_inc(&ring->adev->gpu_reset_counter);

	while (!dma_fence_is_signaled(fence) &&

	       ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)

		ring->funcs->soft_recovery(ring, vmid);



	return dma_fence_is_signaled(fence);

	ret = dma_fence_is_signaled(fence);

	/* increment the counter only if soft reset worked */

	if (ret)

		atomic_inc(&ring->adev->gpu_reset_counter);



	return ret;

}



/*

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+1 −0
Original line number Diff line number Diff line
@@ -4640,6 +4640,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) 
			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));

		/* reset ring buffer */

		ring->wptr = 0;

		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);

		amdgpu_ring_clear_ring(ring);

	}

	return 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

+10 −1
Original line number Diff line number Diff line
@@ -728,7 +728,16 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 
	 * support programmable degamma anywhere.

	 */

	is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;

	drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,

	/* Dont't enable DRM CRTC degamma property for DCN401 since the

	 * pre-blending degamma LUT doesn't apply to cursor, and therefore

	 * can't work similar to a post-blending degamma LUT as in other hw

	 * versions.

	 * TODO: revisit it once KMS plane color API is merged.

	 */

	drm_crtc_enable_color_mgmt(&acrtc->base,

				   (is_dcn &&

				    dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01) ?

				     MAX_COLOR_LUT_ENTRIES : 0,

				   true, MAX_COLOR_LUT_ENTRIES);



	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

+2 −1
Original line number Diff line number Diff line
@@ -1565,7 +1565,7 @@ struct clk_mgr_internal *dcn401_clk_mgr_construct( 
	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);

	if (!clk_mgr->base.bw_params) {

		BREAK_TO_DEBUGGER();

		kfree(clk_mgr);

		kfree(clk_mgr401);

		return NULL;

	}
@@ -1576,6 +1576,7 @@ struct clk_mgr_internal *dcn401_clk_mgr_construct( 
	if (!clk_mgr->wm_range_table) {

		BREAK_TO_DEBUGGER();

		kfree(clk_mgr->base.bw_params);

		kfree(clk_mgr401);

		return NULL;

	}

drivers/gpu/drm/display/drm_dp_helper.c

+1 −1
Original line number Diff line number Diff line
@@ -725,7 +725,7 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 
	 * monitor doesn't power down exactly after the throw away read.

	 */

	if (!aux->is_remote) {

		ret = drm_dp_dpcd_probe(aux, DP_LANE0_1_STATUS);

		ret = drm_dp_dpcd_probe(aux, DP_TRAINING_PATTERN_SET);

		if (ret < 0)

			return ret;

	}