Commit c4969595 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
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clk: renesas: r9a08g045: Drop power domain instantiation 



Since the configuration order between the individual MSTOP and CLKON
bits cannot be preserved with the power domain abstraction, drop the
power domain instantiations.

Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250527112403.1254122-6-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 5cd33db5

drivers/clk/renesas/r9a08g045-cpg.c

+93 −123
Original line number Diff line number Diff line
@@ -192,59 +192,105 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { 
};



static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {

	DEF_MOD("gic_gicclk",		R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0, 0),

	DEF_MOD("ia55_pclk",		R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0, 0),

	DEF_MOD("ia55_clk",		R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1, 0),

	DEF_MOD("dmac_aclk",		R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0, 0),

	DEF_MOD("dmac_pclk",		R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1, 0),

	DEF_MOD("wdt0_pclk",		R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0, 0),

	DEF_MOD("wdt0_clk",		R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1, 0),

	DEF_MOD("sdhi0_imclk",		R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0, 0),

	DEF_MOD("sdhi0_imclk2",		R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1, 0),

	DEF_MOD("sdhi0_clk_hs",		R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2, 0),

	DEF_MOD("sdhi0_aclk",		R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3, 0),

	DEF_MOD("sdhi1_imclk",		R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4, 0),

	DEF_MOD("sdhi1_imclk2",		R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5, 0),

	DEF_MOD("sdhi1_clk_hs",		R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6, 0),

	DEF_MOD("sdhi1_aclk",		R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7, 0),

	DEF_MOD("sdhi2_imclk",		R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8, 0),

	DEF_MOD("sdhi2_imclk2",		R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9, 0),

	DEF_MOD("sdhi2_clk_hs",		R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10, 0),

	DEF_MOD("sdhi2_aclk",		R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11, 0),

	DEF_MOD("ssi0_pclk2",		R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0, 0),

	DEF_MOD("ssi0_sfr",		R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1, 0),

	DEF_MOD("ssi1_pclk2",		R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2, 0),

	DEF_MOD("ssi1_sfr",		R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3, 0),

	DEF_MOD("ssi2_pclk2",		R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4, 0),

	DEF_MOD("ssi2_sfr",		R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5, 0),

	DEF_MOD("ssi3_pclk2",		R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6, 0),

	DEF_MOD("ssi3_sfr",		R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7, 0),

	DEF_MOD("usb0_host",		R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0, 0),

	DEF_MOD("usb1_host",		R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1, 0),

	DEF_MOD("gic_gicclk",		R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0,

					MSTOP(BUS_ACPU, BIT(3))),

	DEF_MOD("ia55_pclk",		R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0,

					MSTOP(BUS_PERI_CPU, BIT(13))),

	DEF_MOD("ia55_clk",		R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1,

					MSTOP(BUS_PERI_CPU, BIT(13))),

	DEF_MOD("dmac_aclk",		R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0,

					MSTOP(BUS_REG1, BIT(2))),

	DEF_MOD("dmac_pclk",		R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1,

					MSTOP(BUS_REG1, BIT(3))),

	DEF_MOD("wdt0_pclk",		R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0,

					MSTOP(BUS_REG0, BIT(0))),

	DEF_MOD("wdt0_clk",		R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1,

					MSTOP(BUS_REG0, BIT(0))),

	DEF_MOD("sdhi0_imclk",		R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0,

					MSTOP(BUS_PERI_COM, BIT(0))),

	DEF_MOD("sdhi0_imclk2",		R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1,

					MSTOP(BUS_PERI_COM, BIT(0))),

	DEF_MOD("sdhi0_clk_hs",		R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2,

					MSTOP(BUS_PERI_COM, BIT(0))),

	DEF_MOD("sdhi0_aclk",		R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3,

					MSTOP(BUS_PERI_COM, BIT(0))),

	DEF_MOD("sdhi1_imclk",		R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4,

					MSTOP(BUS_PERI_COM, BIT(1))),

	DEF_MOD("sdhi1_imclk2",		R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5,

					MSTOP(BUS_PERI_COM, BIT(1))),

	DEF_MOD("sdhi1_clk_hs",		R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6,

					MSTOP(BUS_PERI_COM, BIT(1))),

	DEF_MOD("sdhi1_aclk",		R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7,

					MSTOP(BUS_PERI_COM, BIT(1))),

	DEF_MOD("sdhi2_imclk",		R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8,

					MSTOP(BUS_PERI_COM, BIT(11))),

	DEF_MOD("sdhi2_imclk2",		R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9,

					MSTOP(BUS_PERI_COM, BIT(11))),

	DEF_MOD("sdhi2_clk_hs",		R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10,

					MSTOP(BUS_PERI_COM, BIT(11))),

	DEF_MOD("sdhi2_aclk",		R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11,

					MSTOP(BUS_PERI_COM, BIT(11))),

	DEF_MOD("ssi0_pclk2",		R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0,

					MSTOP(BUS_MCPU1, BIT(10))),

	DEF_MOD("ssi0_sfr",		R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1,

					MSTOP(BUS_MCPU1, BIT(10))),

	DEF_MOD("ssi1_pclk2",		R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2,

					MSTOP(BUS_MCPU1, BIT(11))),

	DEF_MOD("ssi1_sfr",		R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3,

					MSTOP(BUS_MCPU1, BIT(11))),

	DEF_MOD("ssi2_pclk2",		R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4,

					MSTOP(BUS_MCPU1, BIT(12))),

	DEF_MOD("ssi2_sfr",		R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5,

					MSTOP(BUS_MCPU1, BIT(12))),

	DEF_MOD("ssi3_pclk2",		R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6,

					MSTOP(BUS_MCPU1, BIT(13))),

	DEF_MOD("ssi3_sfr",		R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7,

					MSTOP(BUS_MCPU1, BIT(13))),

	DEF_MOD("usb0_host",		R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0,

					MSTOP(BUS_PERI_COM, BIT(5))),

	DEF_MOD("usb1_host",		R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1,

					MSTOP(BUS_PERI_COM, BIT(7))),

	DEF_MOD("usb0_func",		R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2,

					0),

	DEF_MOD("usb_pclk",		R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3, 0),

	DEF_COUPLED("eth0_axi",		R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0, 0),

					MSTOP(BUS_PERI_COM, BIT(6))),

	DEF_MOD("usb_pclk",		R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3,

					MSTOP(BUS_PERI_COM, BIT(4))),

	DEF_COUPLED("eth0_axi",		R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0,

					MSTOP(BUS_PERI_COM, BIT(2))),

	DEF_COUPLED("eth0_chi",		R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0, 0),

	DEF_MOD("eth0_refclk",		R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8, 0),

	DEF_COUPLED("eth1_axi",		R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1, 0),

	DEF_COUPLED("eth1_axi",		R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1,

					MSTOP(BUS_PERI_COM, BIT(3))),

	DEF_COUPLED("eth1_chi",		R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1, 0),

	DEF_MOD("eth1_refclk",		R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9, 0),

	DEF_MOD("i2c0_pclk",		R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0, 0),

	DEF_MOD("i2c1_pclk",		R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1, 0),

	DEF_MOD("i2c2_pclk",		R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2, 0),

	DEF_MOD("i2c3_pclk",		R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3, 0),

	DEF_MOD("scif0_clk_pck",	R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0, 0),

	DEF_MOD("scif1_clk_pck",	R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1, 0),

	DEF_MOD("scif2_clk_pck",	R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2, 0),

	DEF_MOD("scif3_clk_pck",	R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3, 0),

	DEF_MOD("scif4_clk_pck",	R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4, 0),

	DEF_MOD("scif5_clk_pck",	R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5, 0),

	DEF_MOD("i2c0_pclk",		R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0,

					MSTOP(BUS_MCPU2, BIT(10))),

	DEF_MOD("i2c1_pclk",		R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1,

					MSTOP(BUS_MCPU2, BIT(11))),

	DEF_MOD("i2c2_pclk",		R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2,

					MSTOP(BUS_MCPU2, BIT(12))),

	DEF_MOD("i2c3_pclk",		R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3,

					MSTOP(BUS_MCPU2, BIT(13))),

	DEF_MOD("scif0_clk_pck",	R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0,

					MSTOP(BUS_MCPU2, BIT(1))),

	DEF_MOD("scif1_clk_pck",	R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1,

					MSTOP(BUS_MCPU2, BIT(2))),

	DEF_MOD("scif2_clk_pck",	R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2,

					MSTOP(BUS_MCPU2, BIT(3))),

	DEF_MOD("scif3_clk_pck",	R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3,

					MSTOP(BUS_MCPU2, BIT(4))),

	DEF_MOD("scif4_clk_pck",	R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4,

					MSTOP(BUS_MCPU2, BIT(5))),

	DEF_MOD("scif5_clk_pck",	R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5,

					MSTOP(BUS_MCPU3, BIT(4))),

	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, 0),

	DEF_MOD("adc_adclk",		R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0, 0),

	DEF_MOD("adc_pclk",		R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1, 0),

	DEF_MOD("tsu_pclk",		R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0, 0),

	DEF_MOD("vbat_bclk",		R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0, 0),

	DEF_MOD("adc_adclk",		R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0,

					MSTOP(BUS_MCPU2, BIT(14))),

	DEF_MOD("adc_pclk",		R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1,

					MSTOP(BUS_MCPU2, BIT(14))),

	DEF_MOD("tsu_pclk",		R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0,

					MSTOP(BUS_MCPU2, BIT(15))),

	DEF_MOD("vbat_bclk",		R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0,

					MSTOP(BUS_MCPU3, GENMASK(8, 7))),

};



static const struct rzg2l_reset r9a08g045_resets[] = {
@@ -294,78 +340,6 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A08G045_VBAT_BCLK,

};



static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {

	/* Keep always-on domain on the first position for proper domains registration. */

	DEF_PD("always-on",	R9A08G045_PD_ALWAYS_ON,

				DEF_REG_CONF(0, 0),

				GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE),

	DEF_PD("gic",		R9A08G045_PD_GIC,

				DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),

				GENPD_FLAG_ALWAYS_ON),

	DEF_PD("ia55",		R9A08G045_PD_IA55,

				DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),

				GENPD_FLAG_ALWAYS_ON),

	DEF_PD("dmac",		R9A08G045_PD_DMAC,

				DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),

				GENPD_FLAG_ALWAYS_ON),

	DEF_PD("wdt0",		R9A08G045_PD_WDT0,

				DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),

				GENPD_FLAG_IRQ_SAFE),

	DEF_PD("sdhi0",		R9A08G045_PD_SDHI0,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0),

	DEF_PD("sdhi1",		R9A08G045_PD_SDHI1,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0),

	DEF_PD("sdhi2",		R9A08G045_PD_SDHI2,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0),

	DEF_PD("ssi0",		R9A08G045_PD_SSI0,

				DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0),

	DEF_PD("ssi1",		R9A08G045_PD_SSI1,

				DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0),

	DEF_PD("ssi2",		R9A08G045_PD_SSI2,

				DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0),

	DEF_PD("ssi3",		R9A08G045_PD_SSI3,

				DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0),

	DEF_PD("usb0",		R9A08G045_PD_USB0,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0),

	DEF_PD("usb1",		R9A08G045_PD_USB1,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)), 0),

	DEF_PD("usb-phy",	R9A08G045_PD_USB_PHY,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)), 0),

	DEF_PD("eth0",		R9A08G045_PD_ETHER0,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), 0),

	DEF_PD("eth1",		R9A08G045_PD_ETHER1,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), 0),

	DEF_PD("i2c0",		R9A08G045_PD_I2C0,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), 0),

	DEF_PD("i2c1",		R9A08G045_PD_I2C1,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), 0),

	DEF_PD("i2c2",		R9A08G045_PD_I2C2,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), 0),

	DEF_PD("i2c3",		R9A08G045_PD_I2C3,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0),

	DEF_PD("scif0",		R9A08G045_PD_SCIF0,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0),

	DEF_PD("scif1",		R9A08G045_PD_SCIF1,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)), 0),

	DEF_PD("scif2",		R9A08G045_PD_SCIF2,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)), 0),

	DEF_PD("scif3",		R9A08G045_PD_SCIF3,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)), 0),

	DEF_PD("scif4",		R9A08G045_PD_SCIF4,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0),

	DEF_PD("scif5",		R9A08G045_PD_SCIF5,

				DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0),

	DEF_PD("adc",		R9A08G045_PD_ADC,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0),

	DEF_PD("tsu",		R9A08G045_PD_TSU,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0),

	DEF_PD("vbat",		R9A08G045_PD_VBAT,

				DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),

				GENPD_FLAG_ALWAYS_ON),

	DEF_PD("rtc",		R9A08G045_PD_RTC,

				DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), 0),

};



const struct rzg2l_cpg_info r9a08g045_cpg_info = {

	/* Core Clocks */

	.core_clks = r9a08g045_core_clks,
@@ -386,9 +360,5 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = { 
	.resets = r9a08g045_resets,

	.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */



	/* Power domains */

	.pm_domains = r9a08g045_pm_domains,

	.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),



	.has_clk_mon_regs = true,

};