Commit c4b8394e authored by Meenakshikumar Somasundaram's avatar Meenakshikumar Somasundaram Committed by Alex Deucher
Browse files

drm/amd/display: Fix tiled display misalignment 



[Why]
When otg workaround is applied during clock update, otgs of
tiled display went out of sync.

[How]
To call dc_trigger_sync() after clock update to sync otgs again.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 88f4b10a

drivers/gpu/drm/amd/display/dc/core/dc.c

+4 −0
Original line number Diff line number Diff line
@@ -1964,6 +1964,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c 
		wait_for_no_pipes_pending(dc, context);

		/* pplib is notified if disp_num changed */

		dc->hwss.optimize_bandwidth(dc, context);

		/* Need to do otg sync again as otg could be out of sync due to otg

		 * workaround applied during clock update

		 */

		dc_trigger_sync(dc, context);

	}



	if (dc->hwss.update_dsc_pg)