Commit c4c10c01 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Lorenzo Pieralisi
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PCI: cadence: Allow pci_host_bridge to have custom pci_ops 

Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.

Link: https://lore.kernel.org/r/20200722110317.4744-7-kishon@ti.com


Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
parent 40d957e6

drivers/pci/controller/cadence/pcie-cadence-host.c

+2 −1
Original line number Diff line number Diff line
@@ -506,6 +506,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) 
	list_splice_init(&resources, &bridge->windows);

	bridge->dev.parent = dev;

	bridge->busnr = pcie->bus;

	if (!bridge->ops)

		bridge->ops = &cdns_pcie_host_ops;

	bridge->map_irq = of_irq_parse_and_map_pci;

	bridge->swizzle_irq = pci_common_swizzle;