Commit c4d28e06 authored by Andrew Halaney's avatar Andrew Halaney Committed by Martin K. Petersen
Browse files

scsi: ufs: qcom: Perform read back after writing reset bit 

Currently, the reset bit for the UFS provided reset controller (used by its
phy) is written to, and then a mb() happens to try and ensure that hit the
device. Immediately afterwards a usleep_range() occurs.

mb() ensures that the write completes, but completion doesn't mean that it
isn't stored in a buffer somewhere. The recommendation for ensuring this
bit has taken effect on the device is to perform a read back to force it to
make it all the way to the device. This is documented in device-io.rst and
a talk by Will Deacon on this can be seen over here:

    https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678



Let's do that to ensure the bit hits the device. By doing so and
guaranteeing the ordering against the immediately following usleep_range(),
the mb() can safely be removed.

Fixes: 81c0fc51 ("ufs-qcom: add support for Qualcomm Technologies Inc platforms")
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarCan Guo <quic_cang@quicinc.com>
Signed-off-by: default avatarAndrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20240329-ufs-reset-ensure-effect-before-delay-v5-1-181252004586@redhat.com


Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 4cece764

drivers/ufs/host/ufs-qcom.h

+6 −6
Original line number Diff line number Diff line
@@ -151,10 +151,10 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) 
	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1);



	/*

	 * Make sure assertion of ufs phy reset is written to

	 * register before returning

	 * Dummy read to ensure the write takes effect before doing any sort

	 * of delay

	 */

	mb();

	ufshcd_readl(hba, REG_UFS_CFG1);

}



static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
@@ -162,10 +162,10 @@ static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) 
	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1);



	/*

	 * Make sure de-assertion of ufs phy reset is written to

	 * register before returning

	 * Dummy read to ensure the write takes effect before doing any sort

	 * of delay

	 */

	mb();

	ufshcd_readl(hba, REG_UFS_CFG1);

}



/* Host controller hardware version: major.minor.step */